drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

668

TP_PROTO(const struct optc *optc_state, int instance, bool lock, const char *function, const int line),

drivers/gpu/drm/amd/display/dc/core/dc.c

7075

state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7078

state->optc[i].otg_master_enable = 1; /* Active stream */

drivers/gpu/drm/amd/display/dc/core/dc.c

7079

state->optc[i].otg_disable_point_cntl = 0; /* Normal operation */

drivers/gpu/drm/amd/display/dc/core/dc.c

7080

state->optc[i].otg_start_point_cntl = 0; /* Normal start */

drivers/gpu/drm/amd/display/dc/core/dc.c

7081

state->optc[i].otg_field_number_cntl = (timing->flags.INTERLACE) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7082

state->optc[i].otg_out_mux = 0; /* Direct output */

drivers/gpu/drm/amd/display/dc/core/dc.c

7085

state->optc[i].otg_h_total = timing->h_total;

drivers/gpu/drm/amd/display/dc/core/dc.c

7086

state->optc[i].otg_h_blank_start = timing->h_addressable;

drivers/gpu/drm/amd/display/dc/core/dc.c

7087

state->optc[i].otg_h_blank_end = timing->h_total - timing->h_front_porch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7088

state->optc[i].otg_h_sync_start = timing->h_addressable + timing->h_front_porch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7089

state->optc[i].otg_h_sync_end = timing->h_addressable + timing->h_front_porch + timing->h_sync_width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7090

state->optc[i].otg_h_sync_polarity = timing->flags.HSYNC_POSITIVE_POLARITY ? 0 : 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7091

state->optc[i].otg_h_timing_div_mode = (pipe_ctx->next_odm_pipe) ? 1 : 0; /* ODM divide mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7094

state->optc[i].otg_v_total = timing->v_total;

drivers/gpu/drm/amd/display/dc/core/dc.c

7095

state->optc[i].otg_v_blank_start = timing->v_addressable;

drivers/gpu/drm/amd/display/dc/core/dc.c

7096

state->optc[i].otg_v_blank_end = timing->v_total - timing->v_front_porch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7097

state->optc[i].otg_v_sync_start = timing->v_addressable + timing->v_front_porch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7098

state->optc[i].otg_v_sync_end = timing->v_addressable + timing->v_front_porch + timing->v_sync_width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7099

state->optc[i].otg_v_sync_polarity = timing->flags.VSYNC_POSITIVE_POLARITY ? 0 : 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7100

state->optc[i].otg_v_sync_mode = 0; /* Normal sync mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7104

state->optc[i].otg_v_total_max = timing->v_total + 100; /* Typical DRR range */

drivers/gpu/drm/amd/display/dc/core/dc.c

7105

state->optc[i].otg_v_total_min = timing->v_total - 50;

drivers/gpu/drm/amd/display/dc/core/dc.c

7106

state->optc[i].otg_v_total_mid = timing->v_total;

drivers/gpu/drm/amd/display/dc/core/dc.c

7111

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7112

state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7113

state->optc[i].optc_num_of_input_segment = 1; /* 2 segments - 1 */

drivers/gpu/drm/amd/display/dc/core/dc.c

7115

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7116

state->optc[i].optc_seg1_src_sel = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7117

state->optc[i].optc_num_of_input_segment = 0; /* Single segment */

drivers/gpu/drm/amd/display/dc/core/dc.c

7122

state->optc[i].optc_dsc_mode = 1; /* DSC enabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7123

state->optc[i].optc_dsc_bytes_per_pixel = timing->dsc_cfg.bits_per_pixel / 16; /* Convert to bytes */

drivers/gpu/drm/amd/display/dc/core/dc.c

7124

state->optc[i].optc_dsc_slice_width = timing->h_addressable / timing->dsc_cfg.num_slices_h;

drivers/gpu/drm/amd/display/dc/core/dc.c

7126

state->optc[i].optc_dsc_mode = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7127

state->optc[i].optc_dsc_bytes_per_pixel = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7128

state->optc[i].optc_dsc_slice_width = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7132

state->optc[i].otg_stereo_enable = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7133

state->optc[i].otg_interlace_enable = timing->flags.INTERLACE ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7134

state->optc[i].otg_clock_enable = 1; /* OTG clock enabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7135

state->optc[i].vtg0_enable = 1; /* VTG enabled for timing generation */

drivers/gpu/drm/amd/display/dc/core/dc.c

7138

state->optc[i].optc_input_pix_clk_en = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7139

state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable;

drivers/gpu/drm/amd/display/dc/core/dc.c

7140

state->optc[i].otg_vready_offset = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7141

state->optc[i].otg_vstartup_start = timing->v_addressable + 10;

drivers/gpu/drm/amd/display/dc/core/dc.c

7142

state->optc[i].otg_vupdate_offset = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7143

state->optc[i].otg_vupdate_width = 5;

drivers/gpu/drm/amd/display/dc/core/dc.c

7146

memset(&state->optc[i], 0, sizeof(state->optc[i]));

drivers/gpu/drm/amd/display/dc/dc.h

3316

} optc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

798

bool optc: 1;

drivers/gpu/drm/amd/display/dc/dc.h

829

bool optc : 1; /* Output pipe timing combiner */

drivers/gpu/drm/amd/display/dc/dc_trace.h

43

#define TRACE_OPTC_LOCK_UNLOCK_STATE(optc, inst, lock) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

44

trace_dcn_optc_lock_unlock_state(optc, inst, lock, __func__, __LINE__)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

197

struct optc *optc1 = DCN10TG_FROM_TG(tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2532

struct timing_generator *optc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2540

optc = dc->res_pool->timing_generators[dwb->otg_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2541

optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1254

struct timing_generator *optc = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1277

if (optc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1278

if (optc->funcs->optc_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1279

optc->funcs->optc_read_reg_state(optc, out_data->optc_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

672

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

85

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

809

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

91

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

171

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1666

struct timing_generator *optc, struct dc_crtc_timing *timing);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

101

void optc1_program_global_sync(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

108

bool optc1_disable_crtc(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

110

bool optc1_is_counter_moving(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

112

void optc1_get_position(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

115

uint32_t optc1_get_vblank_counter(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

117

void optc1_get_crtc_scanoutpos(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

123

void optc1_set_early_control(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

126

void optc1_wait_for_state(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

129

void optc1_set_blank(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

132

bool optc1_is_blanked(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

134

void optc1_program_blank_color(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

137

bool optc1_did_triggered_reset_occur(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

139

void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

141

void optc1_disable_reset_trigger(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

143

void optc1_lock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

145

void optc1_unlock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

147

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

149

void optc1_set_drr(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

152

void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

154

void optc1_set_static_screen_control(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

158

void optc1_program_stereo(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

162

bool optc1_is_stereo_left_eye(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

164

void optc1_clear_optc_underflow(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

166

void optc1_tg_init(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

168

bool optc1_is_tg_enabled(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

170

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

172

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

174

void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

176

bool optc1_get_otg_active_size(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

180

void optc1_enable_crtc_reset(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

184

bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

186

bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

191

void optc1_set_vtg_params(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

74

void optc1_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

78

bool optc1_validate_timing(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

81

void optc1_program_timing(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

91

void optc1_setup_vertical_interrupt0(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

95

void optc1_setup_vertical_interrupt1(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

98

void optc1_setup_vertical_interrupt2(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

348

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

352

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

355

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

374

bool (*get_otg_active_size)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

412

void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

413

void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

442

void (*set_dwb_source)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

445

void (*get_optc_source)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

465

void (*program_manual_trigger)(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

466

void (*setup_manual_trigger)(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

467

bool (*get_hw_timing)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

470

void (*set_vtg_params)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

473

void (*set_dsc_config)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

477

void (*get_dsc_status)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

479

void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

485

void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

488

void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

489

void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

490

void (*set_gsl_source_select)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

494

void (*set_drr_trigger_window)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

496

void (*set_vtotal_change_limit)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

504

bool (*validate_vmin_vmax)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

506

bool (*validate_vtotal_change_limit)(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

511

void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

513

void (*wait_otg_disable)(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

108

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

112

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

120

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

123

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1230

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1236

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1243

optc1_get_position(optc, &position);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1249

static void optc1_enable_stereo(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1252

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1281

void optc1_program_stereo(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1285

optc1_enable_stereo(optc, timing, flags);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1287

optc1_disable_stereo(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1291

bool optc1_is_stereo_left_eye(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1295

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

130

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

133

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1331

void optc1_read_otg_state(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1334

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1398

bool optc1_get_otg_active_size(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1407

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1429

void optc1_clear_optc_underflow(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1431

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1436

void optc1_tg_init(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1438

optc1_set_blank_data_double_buffer(optc, true);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1439

optc1_set_timing_double_buffer(optc, true);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1440

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1443

bool optc1_is_tg_enabled(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1445

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1454

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1456

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1466

bool optc1_configure_crc(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1469

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1472

if (!optc1_is_tg_enabled(optc))

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1560

bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1564

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

157

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1671

void dcn10_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

177

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

229

optc->funcs->set_vtotal_min_max(optc, v_total, v_total);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

286

optc->funcs->program_global_sync(optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

293

optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

305

if (optc->funcs->is_two_pixels_per_container(&patched_crtc_timing) || optc1->opp_count == 2)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

345

void optc1_set_vtg_params(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

354

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

390

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

392

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

411

void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

413

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

425

static void optc1_unblank_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

427

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

440

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

449

static void optc1_blank_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

451

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

457

optc1_set_blank_data_double_buffer(optc, false);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

460

void optc1_set_blank(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

464

optc1_blank_crtc(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

466

optc1_unblank_crtc(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

469

bool optc1_is_blanked(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

471

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

482

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

484

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

505

if (optc->funcs->is_optc_underflow_occurred(optc) == true)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

506

optc->funcs->clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

523

static bool optc1_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

529

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

535

OPTC_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

555

bool optc1_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

557

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

579

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

582

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

591

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

597

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

64

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

660

uint32_t optc1_get_vblank_counter(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

662

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

671

void optc1_lock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

673

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

676

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

684

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

687

void optc1_unlock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

689

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

694

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

697

void optc1_get_position(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

700

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

71

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

710

bool optc1_is_counter_moving(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

714

optc->funcs->get_position(optc, &position1);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

715

optc->funcs->get_position(optc, &position2);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

725

struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

727

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

739

void optc1_disable_reset_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

741

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

752

void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

754

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

787

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

791

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

831

void optc1_wait_for_state(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

834

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

855

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

865

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

869

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

888

static void optc1_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

890

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

893

MANUAL_FLOW_CONTROL_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

897

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

906

static void optc1_program_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

908

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

924

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

927

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

945

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

95

static void optc1_disable_stereo(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

956

optc->funcs->setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

959

void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

961

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

97

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

971

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

978

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

32

container_of(tg, struct optc, base)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

701

void dcn10_timing_generator_init(struct optc *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

106

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

110

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

132

void optc2_set_dsc_config(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

137

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

152

void optc2_get_dsc_status(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

155

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

161

void optc2_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

164

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

169

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

173

h_div_2 = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

181

void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

184

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

220

void optc2_get_optc_source(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

226

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

243

static void optc2_set_dwb_source(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

246

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

250

OPTC_DWB0_SOURCE_SELECT, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

253

OPTC_DWB1_SOURCE_SELECT, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

265

struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

379

void optc2_triplebuffer_lock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

381

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

384

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

397

void optc2_triplebuffer_unlock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

399

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

409

void optc2_lock_doublebuffer_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

411

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

436

void optc2_lock_doublebuffer_disable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

438

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

452

void optc2_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

454

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

468

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

477

void optc2_program_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

479

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

48

bool optc2_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

485

bool optc2_configure_crc(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

488

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

494

return optc1_configure_crc(optc, params);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

498

void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

500

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

54

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

568

void dcn20_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

60

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

86

void optc2_set_gsl(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

89

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

101

void optc2_set_dsc_config(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

106

void optc2_get_dsc_status(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

109

void optc2_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

112

void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

115

void optc2_get_optc_source(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

120

void optc2_triplebuffer_lock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

121

void optc2_triplebuffer_unlock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

122

void optc2_lock_doublebuffer_disable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

123

void optc2_lock_doublebuffer_enable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

124

void optc2_setup_manual_trigger(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

125

void optc2_program_manual_trigger(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

126

bool optc2_configure_crc(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

87

void dcn20_timing_generator_init(struct optc *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

89

void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

92

bool optc2_enable_crtc(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

94

void optc2_set_gsl(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

97

void optc2_set_gsl_source_select(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

119

static void optc201_get_optc_source(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

124

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

186

void dcn201_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

41

static void optc201_triplebuffer_lock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

43

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

46

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

57

static void optc201_triplebuffer_unlock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

59

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

69

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

75

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

70

void dcn201_timing_generator_init(struct optc *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

102

void optc3_lock_doublebuffer_disable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

104

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

116

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

119

void optc3_lock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

121

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

124

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

132

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

135

void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

137

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

142

void optc3_program_blank_color(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

145

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

158

void optc3_set_drr_trigger_window(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

161

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

168

void optc3_set_vtotal_change_limit(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

171

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

184

void optc3_set_dsc_config(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

189

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

191

optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

195

void optc3_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

198

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

203

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

209

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

218

void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

221

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

275

bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

277

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

288

bool optc3_get_otg_update_pending(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

290

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

301

bool optc3_get_pipe_update_pending(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

303

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

327

static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

329

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

336

void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

338

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

344

void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

346

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

349

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

351

optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

354

void optc3_tg_init(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

356

optc3_set_timing_double_buffer(optc, true);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

357

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

426

void dcn30_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

45

void optc3_triplebuffer_lock(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

47

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

50

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

62

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

65

void optc3_lock_doublebuffer_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

67

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

99

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

330

void dcn30_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

332

void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

334

void optc3_lock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

336

void optc3_lock_doublebuffer_enable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

338

void optc3_lock_doublebuffer_disable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

340

void optc3_set_drr_trigger_window(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

343

void optc3_triplebuffer_lock(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

345

void optc3_program_blank_color(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

348

void optc3_set_vtotal_change_limit(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

351

void optc3_set_dsc_config(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

356

void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

358

void optc3_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

360

void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

362

void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

363

void optc3_tg_init(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

364

void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

365

bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

366

bool optc3_get_otg_update_pending(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

367

bool optc3_get_pipe_update_pending(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

103

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

178

void dcn301_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

53

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

56

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

74

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

83

optc->funcs->setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

92

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

97

void optc301_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

99

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h

32

void dcn301_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h

33

void optc301_setup_manual_trigger(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h

34

void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

101

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

121

static bool optc31_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

123

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

148

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

155

bool optc31_immediate_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

157

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

167

if (optc->ctx->dce_environment != DCE_ENV_DIAG)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

174

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

180

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

183

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

201

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

216

optc->funcs->setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

224

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

228

void optc3_init_odm(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

230

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

234

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

248

void optc31_read_otg_state(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

251

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

318

void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

320

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

43

static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

46

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

513

void dcn31_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

95

static bool optc31_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

97

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

266

void dcn31_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

268

bool optc31_immediate_disable_crtc(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

270

void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

272

void optc3_init_odm(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

274

void optc31_read_otg_state(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

277

void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

105

static bool optc314_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

107

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

111

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

131

static bool optc314_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

133

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

152

static void optc314_phantom_crtc_post_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

154

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

163

static void optc314_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

166

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

171

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

177

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

186

static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

188

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

262

void dcn314_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

50

static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

53

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

260

void dcn314_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

102

struct optc *optc1 = DCN10TG_FROM_TG(tg);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

126

struct optc *optc1 = DCN10TG_FROM_TG(tg);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

131

void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

133

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

145

static bool optc32_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

147

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

151

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

171

static bool optc32_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

173

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

202

static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

204

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

213

static void optc32_disable_phantom_otg(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

215

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

227

void optc32_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

230

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

235

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

241

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

250

static void optc32_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

252

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

253

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

256

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

273

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

276

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

294

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

297

optc32_setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

371

void dcn32_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

45

static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

48

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h

188

void dcn32_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h

189

void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h

191

void optc32_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

112

static bool optc35_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

114

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

118

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

138

static bool optc35_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

140

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

167

optc1_clear_optc_underflow(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

172

static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

174

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

206

static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

210

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

273

bool optc35_configure_crc(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

276

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

279

if (!optc1_is_tg_enabled(optc))

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

366

static void optc35_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

368

if (!optc || !optc->ctx)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

371

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

372

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

375

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

390

if (optc->funcs && optc->funcs->setup_manual_trigger)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

391

optc->funcs->setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

396

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

399

if (!optc || !params)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

402

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

421

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

422

optc->funcs->set_vtotal_min_max(optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

424

optc35_setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

432

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

433

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

441

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

444

if (!optc || !params)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

447

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

461

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

462

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

473

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

474

optc->funcs->set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

493

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

494

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

516

if (optc->funcs && optc->funcs->set_vtotal_min_max)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

517

optc->funcs->set_vtotal_min_max(optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

519

optc35_setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

527

void optc35_wait_otg_disable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

529

struct optc *optc1;

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

532

if (!optc || !optc->ctx)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

535

optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

58

static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

61

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

611

void dcn35_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

626

optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

629

void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

100

void optc35_wait_otg_disable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

87

void dcn35_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

89

void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

91

void optc35_set_drr(struct timing_generator *optc, const struct drr_params *params);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

94

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

97

bool optc35_configure_crc(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

104

void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

107

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

165

void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

167

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

180

bool optc401_enable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

182

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

186

OPTC_SEG0_SRC_SEL, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

206

bool optc401_disable_crtc(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

208

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

242

void optc401_phantom_crtc_post_enable(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

244

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

253

void optc401_disable_phantom_otg(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

255

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

267

void optc401_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

270

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

275

OPTC_SEG0_SRC_SEL, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

281

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

291

void optc401_setup_manual_trigger(struct timing_generator *optc)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

293

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

294

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

298

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

315

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

318

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

319

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

336

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

359

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

360

optc401_setup_manual_trigger(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

368

optc->funcs->set_vtotal_min_max(optc, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

373

void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

375

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

384

void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

386

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

390

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

398

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

400

optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

405

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

412

struct optc *optc1 = DCN10TG_FROM_TG(optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

440

struct optc *optc1 = DCN10TG_FROM_TG(tg);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

452

struct optc *optc1 = DCN10TG_FROM_TG(tg);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

539

void dcn401_timing_generator_init(struct optc *optc1)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

169

void dcn401_timing_generator_init(struct optc *optc1);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

172

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

174

void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

175

void optc401_setup_manual_trigger(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

177

struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

183

bool optc401_enable_crtc(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

184

bool optc401_disable_crtc(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

185

void optc401_phantom_crtc_post_enable(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

186

void optc401_disable_phantom_otg(struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

187

void optc401_set_odm_bypass(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

189

void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

191

void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

192

void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

734

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

735

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

913

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

914

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

790

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

791

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1071

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1072

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

921

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

922

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

877

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

878

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

637

struct optc *tgn10 = kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

609

struct optc *tgn10 = kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1087

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1088

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

901

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1145

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1146

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

921

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1086

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1087

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

901

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1079

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1080

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

896

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1030

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1031

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

729

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1024

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1025

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

725

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1064

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1065

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

759

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1044

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1045

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

739

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1051

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1052

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

746

.optc = true,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1026

struct optc *tgn10 =

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1027

kzalloc_obj(struct optc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

723

.optc = true,