drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

274

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

275

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

276

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

277

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

278

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

279

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

280

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

694

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

303

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

304

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

305

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

306

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

307

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

308

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

309

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

718

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

312

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

313

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

314

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

315

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

316

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

317

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

318

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

694

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

321

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

322

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

323

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

324

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

325

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

326

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

327

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

437

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

291

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

292

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

293

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

294

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

295

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

296

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

297

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

530

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

290

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

291

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

292

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

293

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

294

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

295

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

296

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

536

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

319

static const struct dcn10_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

320

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

321

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

322

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

323

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

644

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

380

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

381

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

382

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

383

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

384

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

385

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

386

opp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

810

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

440

static const struct dcn201_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

441

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

442

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

676

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1064

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

242

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

243

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

244

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

245

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

246

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

247

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

248

opp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

442

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

443

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

444

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

445

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

446

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

447

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

448

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

783

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

429

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

430

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

431

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

432

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

433

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

746

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

587

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

588

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

589

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

590

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

591

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

592

opp_regs(4)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

612

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

565

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

566

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

567

opp_regs(1)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

587

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

502

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

503

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

504

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

505

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

506

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

964

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1000

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

508

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

509

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

510

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

511

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

512

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

505

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

506

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

507

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

508

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

509

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

963

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

496

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

497

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

498

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

499

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

500

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

956

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1014

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1021

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

384

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1008

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1015

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

383

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

402

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

866

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

873

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

382

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

846

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

853

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

383

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

853

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

860

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1010

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1017

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

363

static struct dcn20_opp_registers opp_regs[4];