opera1_xilinx_rw
ret = opera1_xilinx_rw(dev->udev, request,
return opera1_xilinx_rw(d->udev, 0xb7, val,
ret = opera1_xilinx_rw(d->udev, 0xb1, 0xa0, command, 1, OPERA_WRITE_MSG);
ret = opera1_xilinx_rw(d->udev, 0xb1, 0xa1, mac, 6, OPERA_READ_MSG);
opera1_xilinx_rw(dev, 0xbc, 0x00, &testval, 1, OPERA_READ_MSG);
opera1_xilinx_rw(dev, 0xbc, 0xaa, &fpga_command, 1,
if (opera1_xilinx_rw
if (ret || opera1_xilinx_rw