arch/powerpc/platforms/powernv/opal-irqchip.c

102

static struct opal_event_irqchip opal_event_irqchip = {

arch/powerpc/platforms/powernv/opal-irqchip.c

115

irq_set_chip_data(irq, &opal_event_irqchip);

arch/powerpc/platforms/powernv/opal-irqchip.c

116

irq_set_chip_and_handler(irq, &opal_event_irqchip.irqchip,

arch/powerpc/platforms/powernv/opal-irqchip.c

194

opal_event_irqchip.domain = irq_domain_create_linear(of_fwnode_handle(dn),

arch/powerpc/platforms/powernv/opal-irqchip.c

196

&opal_event_domain_ops, &opal_event_irqchip);

arch/powerpc/platforms/powernv/opal-irqchip.c

198

if (!opal_event_irqchip.domain) {

arch/powerpc/platforms/powernv/opal-irqchip.c

309

if (WARN_ON_ONCE(!opal_event_irqchip.domain))

arch/powerpc/platforms/powernv/opal-irqchip.c

312

return irq_create_mapping(opal_event_irqchip.domain, opal_event_nr);

arch/powerpc/platforms/powernv/opal-irqchip.c

36

static struct opal_event_irqchip opal_event_irqchip;

arch/powerpc/platforms/powernv/opal-irqchip.c

46

e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask;

arch/powerpc/platforms/powernv/opal-irqchip.c

56

generic_handle_domain_irq(opal_event_irqchip.domain, hwirq);

arch/powerpc/platforms/powernv/opal-irqchip.c

65

e = be64_to_cpu(events) & opal_event_irqchip.mask;

arch/powerpc/platforms/powernv/opal-irqchip.c

72

if (READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask)

arch/powerpc/platforms/powernv/opal-irqchip.c

79

clear_bit(d->hwirq, &opal_event_irqchip.mask);

arch/powerpc/platforms/powernv/opal-irqchip.c

84

set_bit(d->hwirq, &opal_event_irqchip.mask);