drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

61

if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

158

u32 disp = nvkm_falcon_rd32(falcon, 0x01c);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

159

u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

267

reg = nvkm_falcon_rd32(falcon, 0x12c);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

273

reg = nvkm_falcon_rd32(falcon, 0x108);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

278

u32 val = nvkm_falcon_rd32(falcon, func->debug);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

28

u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

29

u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

84

cmdq->position = nvkm_falcon_rd32(falcon, cmdq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

100

if ((nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000010) != 0x00000000) {

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

103

if (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000001)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

30

return (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x388) & 0x00000080) != 0;

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

36

return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

75

if (!(nvkm_falcon_rd32(falcon, 0x0f4) & 0x00001000))

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

86

nvkm_falcon_rd32(falcon, 0x0f4);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

89

if (nvkm_falcon_rd32(falcon, 0x0f4) & 0x80000000)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

125

if (intr && !(nvkm_falcon_rd32(falcon, 0x008) & 0x00000008))

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

128

return (nvkm_falcon_rd32(falcon, 0x0dc) & 0x00007000) >> 12;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

146

if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006))

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

232

if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

237

mbox0 = nvkm_falcon_rd32(falcon, 0x040);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

238

mbox1 = nvkm_falcon_rd32(falcon, 0x044);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

31

u32 sctl = nvkm_falcon_rd32(falcon, 0x240);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

32

u32 tidx = nvkm_falcon_rd32(falcon, 0x148);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

335

if (nvkm_falcon_rd32(falcon, addr) & 0x00100000) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

38

ip = nvkm_falcon_rd32(falcon, 0x14c);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

47

*(u32 *)img = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

54

u32 data = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

28

*(u32 *)img = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

163

msgq->offset = nvkm_falcon_rd32(falcon, falcon->func->msgq.tail);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

29

msgq->position = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

46

u32 head = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

47

u32 tail = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

57

head = nvkm_falcon_rd32(falcon, msgq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/tu102.c

27

return (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x240) & 0x00000001) != 0;

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

95

u32 reg = nvkm_falcon_rd32(falcon, 0x100);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

32

u32 data = nvkm_falcon_rd32(falcon, falcon->addr2 + NV_PRISCV_RISCV_CPUCTL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

49

*mbox0 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX0);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

56

u32 mbox1 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX1);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

64

data = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_HWCFG2);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1080

if (nvkm_falcon_rd32(&gsp->falcon, 0x100) & 0x00000040)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1088

if (nvkm_falcon_rd32(&gsp->falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1113

mbox0 = nvkm_falcon_rd32(&sec2->falcon, 0x040);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1773

if (nvkm_falcon_rd32(&gsp->falcon, 0x040) == 0x80000000)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

64

u32 intr = nvkm_falcon_rd32(&gsp->falcon, 0x0008);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

65

u32 inte = nvkm_falcon_rd32(&gsp->falcon, gsp->falcon.func->addr2 +

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

100

status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10));

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

101

status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10));

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

30

return (nvkm_falcon_rd32(falcon, 0x20c) & 0x00007000) >> 12;