arch/arc/include/asm/atomic64-arcv2.h

115

#define ATOMIC64_OPS(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

116

ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

117

ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

118

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arc/include/asm/atomic64-arcv2.h

124

#define ATOMIC64_OPS(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

125

ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

126

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arc/include/asm/atomic64-arcv2.h

49

#define ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

58

" " #op2 " %H0, %H0, %H2 \n" \

arch/arc/include/asm/atomic64-arcv2.h

66

#define ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

75

" " #op2 " %H0, %H0, %H2 \n" \

arch/arc/include/asm/atomic64-arcv2.h

88

#define ATOMIC64_FETCH_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

97

" " #op2 " %H1, %H0, %H3 \n" \

arch/arm/include/asm/atomic.h

311

#define ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

321

" " #op2 " %R0, %R0, %R4\n" \

arch/arm/include/asm/atomic.h

330

#define ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arm/include/asm/atomic.h

342

" " #op2 " %R0, %R0, %R4\n" \

arch/arm/include/asm/atomic.h

353

#define ATOMIC64_FETCH_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

365

" " #op2 " %R1, %R0, %R5\n" \

arch/arm/include/asm/atomic.h

376

#define ATOMIC64_OPS(op, op1, op2) \

arch/arm/include/asm/atomic.h

377

ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

378

ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arm/include/asm/atomic.h

379

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arm/include/asm/atomic.h

390

#define ATOMIC64_OPS(op, op1, op2) \

arch/arm/include/asm/atomic.h

391

ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

392

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arm/include/asm/hardware/cp14.h

17

#define MRC14(op1, crn, crm, op2) \

arch/arm/include/asm/hardware/cp14.h

20

asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \

arch/arm/include/asm/hardware/cp14.h

24

#define MCR14(val, op1, crn, crm, op2) \

arch/arm/include/asm/hardware/cp14.h

26

asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\

arch/arm64/include/asm/esr.h

235

#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \

arch/arm64/include/asm/esr.h

238

((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \

arch/arm64/include/asm/esr.h

351

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

arch/arm64/include/asm/esr.h

353

((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \

arch/arm64/include/asm/sysreg.h

117

#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \

arch/arm64/include/asm/sysreg.h

119

sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \

arch/arm64/include/asm/sysreg.h

40

#define sys_reg(op0, op1, crn, crm, op2) \

arch/arm64/include/asm/sysreg.h

428

#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))

arch/arm64/include/asm/sysreg.h

43

((op2) << Op2_shift))

arch/arm64/include/asm/sysreg.h

92

#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)

arch/arm64/include/uapi/asm/kvm.h

247

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \

arch/arm64/include/uapi/asm/kvm.h

253

ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

arch/arm64/include/uapi/asm/kvm.h

545

#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \

arch/arm64/include/uapi/asm/kvm.h

549

(__op1 << 6 | ((crm) & 7) << 3 | (op2)); \

arch/arm64/kvm/emulate-nested.c

2102

op2 = sys_reg_Op2(encoding);

arch/arm64/kvm/emulate-nested.c

2104

if (op2 < Op2_mask)

arch/arm64/kvm/hyp/nvhe/sys_regs.c

373

#define ID_UNALLOCATED(crm, op2) { \

arch/arm64/kvm/hyp/nvhe/sys_regs.c

374

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/arm64/kvm/sys_regs.c

2645

#define ID_UNALLOCATED(crm, op2) { \

arch/arm64/kvm/sys_regs.c

2646

.name = "S3_0_0_" #crm "_" #op2, \

arch/arm64/kvm/sys_regs.c

2647

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/mips/kernel/traps.c

727

int op2 = opcode & CSR_OPCODE2_MASK;

arch/mips/kernel/traps.c

730

if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {

arch/powerpc/math-emu/math.c

228

void *op0 = NULL, *op1 = NULL, *op2 = NULL, *op3 = NULL;

arch/powerpc/math-emu/math.c

28

#define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \

arch/powerpc/math-emu/math.c

334

op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);

arch/powerpc/math-emu/math.c

340

op2 = (void *)&current->thread.TS_FPR((insn >> 6) & 0x1f);

arch/powerpc/math-emu/math.c

346

op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);

arch/powerpc/math-emu/math.c

400

op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);

arch/powerpc/math-emu/math.c

407

op2 = (void *)(long)((insn >> 18) & 0x7);

arch/powerpc/math-emu/math.c

435

eflag = func(op0, op1, op2, op3);

arch/s390/include/asm/percpu.h

58

#define arch_this_cpu_add(pcp, val, op1, op2, szcast) \

arch/s390/include/asm/percpu.h

68

op2 " %[ptr__],%[val__]" \

arch/s390/kvm/priv.c

89

u64 op2;

arch/s390/kvm/priv.c

96

op2 = kvm_s390_get_base_disp_s(vcpu, &ar);

arch/s390/kvm/priv.c

97

if (op2 & 7) /* Operand must be on a doubleword boundary */

arch/s390/kvm/priv.c

99

rc = read_guest(vcpu, op2, ar, &gtod.tod, sizeof(gtod.tod));

arch/s390/net/bpf_jit_comp.c

217

#define _EMIT6(op1, op2) \

arch/s390/net/bpf_jit_comp.c

221

*(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \

arch/s390/net/bpf_jit_comp.c

226

#define _EMIT6_DISP(op1, op2, disp) \

arch/s390/net/bpf_jit_comp.c

229

_EMIT6((op1) | __disp, op2); \

arch/s390/net/bpf_jit_comp.c

232

#define _EMIT6_DISP_LH(op1, op2, disp) \

arch/s390/net/bpf_jit_comp.c

237

_EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \

arch/s390/net/bpf_jit_comp.c

240

#define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \

arch/s390/net/bpf_jit_comp.c

243

reg_high(b3) << 8, op2, disp); \

arch/s390/net/bpf_jit_comp.c

249

#define EMIT6_PCREL_RIEB(op1, op2, b1, b2, mask, target) \

arch/s390/net/bpf_jit_comp.c

253

(op2) | (mask) << 12); \

arch/s390/net/bpf_jit_comp.c

258

#define EMIT6_PCREL_RIEC(op1, op2, b1, imm, mask, target) \

arch/s390/net/bpf_jit_comp.c

262

(rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \

arch/s390/net/bpf_jit_comp.c

267

#define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \

arch/s390/net/bpf_jit_comp.c

270

_EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\

arch/sh/kernel/kprobes.c

144

struct kprobe *op1, *op2;

arch/sh/kernel/kprobes.c

149

op2 = this_cpu_ptr(&saved_next_opcode2);

arch/sh/kernel/kprobes.c

173

op2->addr =

arch/sh/kernel/kprobes.c

175

op2->opcode = *(op2->addr);

arch/sh/kernel/kprobes.c

176

arch_arm_kprobe(op2);

arch/sh/kernel/kprobes.c

183

op2->addr =

arch/sh/kernel/kprobes.c

185

op2->opcode = *(op2->addr);

arch/sh/kernel/kprobes.c

186

arch_arm_kprobe(op2);

arch/sparc/kernel/uprobes.c

62

u32 op2 = (insn >> 22) & 0x7;

arch/sparc/kernel/uprobes.c

65

(op2 == 1 || op2 == 2 || op2 == 3 || op2 == 5 || op2 == 6) &&

arch/x86/kernel/alternative.c

1004

if (op2 >= 0x80 && op2 <= 0x8f)

arch/x86/kernel/alternative.c

977

u8 op1, op2;

arch/x86/kernel/alternative.c

985

op2 = insn.opcode.bytes[1];

arch/x86/kvm/svm/svm_ops.h

29

#define svm_asm2(insn, op1, op2, clobber...) \

arch/x86/kvm/svm/svm_ops.h

33

:: op1, op2 : clobber : fault); \

arch/x86/kvm/vmx/vmx_ops.h

208

#define vmx_asm2(insn, op1, op2, error_args...) \

arch/x86/kvm/vmx/vmx_ops.h

214

: : op1, op2 : "cc" : error, fault); \

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

345

#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

348

#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

349

#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

357

#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

358

#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

58

#define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

60

REG_FIELD_PREP(GENMASK(9, 0), (op2)))

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

62

#define __CS_ALU_INSTR(opcode, op1, op2) CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

64

CS_ALU_OPERAND_##op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

67

#define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

68

#define CS_ALU_INSTR_LOADINV(op1, op2) __CS_ALU_INSTR(LOADINV, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

76

#define CS_ALU_INSTR_STORE(op1, op2) __CS_ALU_INSTR(STORE, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

77

#define CS_ALU_INSTR_STOREINV(op1, op2) __CS_ALU_INSTR(STOREINV, op1, op2)

drivers/gpu/host1x/cdma.c

138

static void host1x_pushbuffer_push(struct push_buffer *pb, u32 op1, u32 op2)

drivers/gpu/host1x/cdma.c

144

*(p++) = op2;

drivers/gpu/host1x/cdma.c

590

void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2)

drivers/gpu/host1x/cdma.c

597

op1, op2);

drivers/gpu/host1x/cdma.c

605

host1x_pushbuffer_push(pb, op1, op2);

drivers/gpu/host1x/cdma.c

617

void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,

drivers/gpu/host1x/cdma.c

626

trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2,

drivers/gpu/host1x/cdma.c

650

host1x_pushbuffer_push(pb, op1, op2);

drivers/gpu/host1x/cdma.h

83

void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);

drivers/gpu/host1x/cdma.h

84

void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,

drivers/gpu/host1x/hw/channel_hw.c

134

u32 op2, op3;

drivers/gpu/host1x/hw/channel_hw.c

136

op2 = lower_32_bits(addr);

drivers/gpu/host1x/hw/channel_hw.c

146

host1x_cdma_push_wide(cdma, op1, op2, op3, op4);

drivers/gpu/host1x/hw/channel_hw.c

155

host1x_cdma_push(cdma, op1, op2);

drivers/iommu/msm_iommu.c

28

#define MRC(reg, processor, op1, crn, crm, op2) \

drivers/iommu/msm_iommu.c

30

" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

13

u16 qm_mulu16(u16 op1, u16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

15

return (u16) (((u32) op1 * (u32) op2) >> 16);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

26

s16 qm_muls16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

29

if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

32

result = ((s32) (op1) * (s32) (op2));

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

42

s32 qm_add32(s32 op1, s32 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

45

result = op1 + op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

46

if (op1 < 0 && op2 < 0 && result > 0)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

48

else if (op1 > 0 && op2 > 0 && result < 0)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

59

s16 qm_add16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

62

s32 temp = (s32) op1 + (s32) op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

78

s16 qm_sub16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

81

s32 temp = (s32) op1 - (s32) op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

11

u16 qm_mulu16(u16 op1, u16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

13

s16 qm_muls16(s16 op1, s16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

15

s32 qm_add32(s32 op1, s32 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

17

s16 qm_add16(s16 op1, s16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

19

s16 qm_sub16(s16 op1, s16 op2);

drivers/platform/x86/lenovo/ideapad-laptop.c

2042

unsigned long op1, op2;

drivers/platform/x86/lenovo/ideapad-laptop.c

2051

op2 = SBMC_RAPID_CHARGE_ON;

drivers/platform/x86/lenovo/ideapad-laptop.c

2055

op2 = SBMC_CONSERVATION_ON;

drivers/platform/x86/lenovo/ideapad-laptop.c

2059

op2 = SBMC_CONSERVATION_OFF;

drivers/platform/x86/lenovo/ideapad-laptop.c

2074

return exec_sbmc(priv->adev->handle, op2);

fs/smb/server/oplock.c

1038

static void copy_lease(struct oplock_info *op1, struct oplock_info *op2)

fs/smb/server/oplock.c

1041

struct lease *lease2 = op2->o_lease;

fs/smb/server/oplock.c

1043

op2->level = op1->level;

include/linux/pds/pds_adminq.h

1275

#define PDS_FWCTL_RPC_OPCODE_CMP(op1, op2) \

include/linux/pds/pds_adminq.h

1276

(PDS_FWCTL_RPC_OPCODE_GET_CMD(op1) == PDS_FWCTL_RPC_OPCODE_GET_CMD(op2) && \

include/linux/pds/pds_adminq.h

1277

PDS_FWCTL_RPC_OPCODE_GET_VER(op1) <= PDS_FWCTL_RPC_OPCODE_GET_VER(op2))

include/trace/events/host1x.h

50

TP_PROTO(const char *name, u32 op1, u32 op2),

include/trace/events/host1x.h

52

TP_ARGS(name, op1, op2),

include/trace/events/host1x.h

57

__field(u32, op2)

include/trace/events/host1x.h

63

__entry->op2 = op2;

include/trace/events/host1x.h

67

__entry->name, __entry->op1, __entry->op2)

include/trace/events/host1x.h

71

TP_PROTO(const char *name, u32 op1, u32 op2, u32 op3, u32 op4),

include/trace/events/host1x.h

73

TP_ARGS(name, op1, op2, op3, op4),

include/trace/events/host1x.h

78

__field(u32, op2)

include/trace/events/host1x.h

86

__entry->op2 = op2;

include/trace/events/host1x.h

92

__entry->name, __entry->op1, __entry->op2, __entry->op3,

lib/zlib_dfltcc/dfltcc_util.h

34

const Byte **op2,

lib/zlib_dfltcc/dfltcc_util.h

42

const Byte *t4 = op2 ? *op2 : NULL;

lib/zlib_dfltcc/dfltcc_util.h

94

if (op2)

lib/zlib_dfltcc/dfltcc_util.h

95

*op2 = t4;

lib/zstd/decompress/huf_decompress.c

1414

BYTE* op2 = opStart2;

lib/zstd/decompress/huf_decompress.c

1437

HUF_DECODE_SYMBOLX2_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1438

HUF_DECODE_SYMBOLX2_1(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1439

HUF_DECODE_SYMBOLX2_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1440

HUF_DECODE_SYMBOLX2_0(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1455

HUF_DECODE_SYMBOLX2_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1459

HUF_DECODE_SYMBOLX2_1(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1463

HUF_DECODE_SYMBOLX2_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1467

HUF_DECODE_SYMBOLX2_0(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

1481

if (op2 > opStart3) return ERROR(corruption_detected);

lib/zstd/decompress/huf_decompress.c

1487

HUF_decodeStreamX2(op2, &bitD2, opStart3, dt, dtLog);

lib/zstd/decompress/huf_decompress.c

633

BYTE* op2 = opStart2;

lib/zstd/decompress/huf_decompress.c

652

HUF_DECODE_SYMBOLX1_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

656

HUF_DECODE_SYMBOLX1_1(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

660

HUF_DECODE_SYMBOLX1_2(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

664

HUF_DECODE_SYMBOLX1_0(op2, &bitD2);

lib/zstd/decompress/huf_decompress.c

678

if (op2 > opStart3) return ERROR(corruption_detected);

lib/zstd/decompress/huf_decompress.c

684

HUF_decodeStreamX1(op2, &bitD2, opStart3, dt, dtLog);

scripts/gcc-plugins/gcc-common.h

315

static inline gimple gimple_build_assign_with_ops(enum tree_code subcode, tree lhs, tree op1, tree op2 MEM_STAT_DECL)

scripts/gcc-plugins/gcc-common.h

317

return gimple_build_assign(lhs, subcode, op1, op2 PASS_MEM_STAT);

scripts/gcc-plugins/latent_entropy_plugin.c

335

tree op2)

scripts/gcc-plugins/latent_entropy_plugin.c

337

return gimple_build_assign_with_ops(code, lhs, op1, op2);

tools/arch/arm64/include/asm/esr.h

217

#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \

tools/arch/arm64/include/asm/esr.h

220

((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \

tools/arch/arm64/include/asm/esr.h

333

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

tools/arch/arm64/include/asm/esr.h

335

((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \

tools/arch/arm64/include/asm/sysreg.h

115

#define __SYS_BARRIER_INSN(CRm, op2, Rt) \

tools/arch/arm64/include/asm/sysreg.h

116

__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))

tools/arch/arm64/include/asm/sysreg.h

39

#define sys_reg(op0, op1, crn, crm, op2) \

tools/arch/arm64/include/asm/sysreg.h

42

((op2) << Op2_shift))

tools/arch/arm64/include/asm/sysreg.h

443

#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))

tools/arch/arm64/include/asm/sysreg.h

91

#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)

tools/arch/arm64/include/uapi/asm/kvm.h

247

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \

tools/arch/arm64/include/uapi/asm/kvm.h

253

ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

tools/arch/arm64/include/uapi/asm/kvm.h

545

#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \

tools/arch/arm64/include/uapi/asm/kvm.h

549

(__op1 << 6 | ((crm) & 7) << 3 | (op2)); \

tools/objtool/arch/x86/decode.c

225

unsigned char op1, op2, op3, prefix,

tools/objtool/arch/x86/decode.c

253

op2 = ins.opcode.bytes[1];

tools/objtool/arch/x86/decode.c

572

if (op2 == 0x01) {

tools/objtool/arch/x86/decode.c

588

} else if (op2 >= 0x80 && op2 <= 0x8f) {

tools/objtool/arch/x86/decode.c

592

} else if (op2 == 0x05 || op2 == 0x34) {

tools/objtool/arch/x86/decode.c

597

} else if (op2 == 0x07 || op2 == 0x35) {

tools/objtool/arch/x86/decode.c

602

} else if (op2 == 0x0b || op2 == 0xb9) {

tools/objtool/arch/x86/decode.c

607

} else if (op2 == 0x1f) {

tools/objtool/arch/x86/decode.c

613

} else if (op2 == 0x1e) {

tools/objtool/arch/x86/decode.c

619

} else if (op2 == 0x38 && op3 == 0xf8) {

tools/objtool/arch/x86/decode.c

626

} else if (op2 == 0xa0 || op2 == 0xa8) {

tools/objtool/arch/x86/decode.c

634

} else if (op2 == 0xa1 || op2 == 0xa9) {

tools/perf/arch/x86/util/cpuid.h

29

: "a"(op), "2"(op2));

tools/perf/arch/x86/util/cpuid.h

7

cpuid(unsigned int op, unsigned int op2, unsigned int *a, unsigned int *b,

tools/testing/selftests/kvm/arm64/get-reg-list.c

214

unsigned op0, op1, crn, crm, op2;

tools/testing/selftests/kvm/arm64/get-reg-list.c

268

op2 = (id & KVM_REG_ARM64_SYSREG_OP2_MASK) >> KVM_REG_ARM64_SYSREG_OP2_SHIFT;

tools/testing/selftests/kvm/arm64/get-reg-list.c

269

TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2),

tools/testing/selftests/kvm/arm64/get-reg-list.c

271

printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2);

tools/testing/selftests/sgx/test_encl.c

101

struct encl_op_get_from_buf *op2 = op;

tools/testing/selftests/sgx/test_encl.c

103

memcpy(&op2->value, &encl_buffer[0], 8);

tools/testing/selftests/sgx/test_encl.c

94

struct encl_op_put_to_buf *op2 = op;

tools/testing/selftests/sgx/test_encl.c

96

memcpy(&encl_buffer[0], &op2->value, 8);