arch/arc/include/asm/atomic64-arcv2.h

115

#define ATOMIC64_OPS(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

116

ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

117

ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

118

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arc/include/asm/atomic64-arcv2.h

124

#define ATOMIC64_OPS(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

125

ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

126

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arc/include/asm/atomic64-arcv2.h

49

#define ATOMIC64_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

57

" " #op1 " %L0, %L0, %L2 \n" \

arch/arc/include/asm/atomic64-arcv2.h

66

#define ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

74

" " #op1 " %L0, %L0, %L2 \n" \

arch/arc/include/asm/atomic64-arcv2.h

88

#define ATOMIC64_FETCH_OP(op, op1, op2) \

arch/arc/include/asm/atomic64-arcv2.h

96

" " #op1 " %L1, %L0, %L3 \n" \

arch/arm/include/asm/atomic.h

311

#define ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

320

" " #op1 " %Q0, %Q0, %Q4\n" \

arch/arm/include/asm/atomic.h

330

#define ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arm/include/asm/atomic.h

341

" " #op1 " %Q0, %Q0, %Q4\n" \

arch/arm/include/asm/atomic.h

353

#define ATOMIC64_FETCH_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

364

" " #op1 " %Q1, %Q0, %Q5\n" \

arch/arm/include/asm/atomic.h

376

#define ATOMIC64_OPS(op, op1, op2) \

arch/arm/include/asm/atomic.h

377

ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

378

ATOMIC64_OP_RETURN(op, op1, op2) \

arch/arm/include/asm/atomic.h

379

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arm/include/asm/atomic.h

390

#define ATOMIC64_OPS(op, op1, op2) \

arch/arm/include/asm/atomic.h

391

ATOMIC64_OP(op, op1, op2) \

arch/arm/include/asm/atomic.h

392

ATOMIC64_FETCH_OP(op, op1, op2)

arch/arm/include/asm/hardware/cp14.h

17

#define MRC14(op1, crn, crm, op2) \

arch/arm/include/asm/hardware/cp14.h

20

asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \

arch/arm/include/asm/hardware/cp14.h

24

#define MCR14(val, op1, crn, crm, op2) \

arch/arm/include/asm/hardware/cp14.h

26

asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\

arch/arm64/include/asm/esr.h

235

#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \

arch/arm64/include/asm/esr.h

237

((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \

arch/arm64/include/asm/esr.h

351

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

arch/arm64/include/asm/esr.h

352

(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \

arch/arm64/include/asm/esr.h

372

#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \

arch/arm64/include/asm/esr.h

373

(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \

arch/arm64/include/asm/sysreg.h

117

#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \

arch/arm64/include/asm/sysreg.h

119

sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \

arch/arm64/include/asm/sysreg.h

40

#define sys_reg(op0, op1, crn, crm, op2) \

arch/arm64/include/asm/sysreg.h

41

(((op0) << Op0_shift) | ((op1) << Op1_shift) | \

arch/arm64/include/asm/sysreg.h

92

#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)

arch/arm64/include/uapi/asm/kvm.h

247

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \

arch/arm64/include/uapi/asm/kvm.h

250

ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \

arch/arm64/include/uapi/asm/kvm.h

545

#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \

arch/arm64/include/uapi/asm/kvm.h

547

__u64 __op1 = (op1) & 3; \

arch/arm64/kvm/emulate-nested.c

2099

op1 = sys_reg_Op1(encoding);

arch/arm64/kvm/emulate-nested.c

2110

if (op1 < Op1_mask)

arch/powerpc/include/asm/mpc52xx_psc.h

203

u8 op1; /* PSC + 0x38 */

arch/powerpc/include/asm/mpc52xx_psc.h

344

u8 op1; /* PSC + 0x48 */

arch/powerpc/kernel/trace/ftrace_64_pg.c

396

static bool expected_nop_sequence(void *ip, ppc_inst_t op0, ppc_inst_t op1)

arch/powerpc/kernel/trace/ftrace_64_pg.c

402

ppc_inst_equal(op1, ppc_inst(PPC_INST_LD_TOC));

arch/powerpc/math-emu/math.c

228

void *op0 = NULL, *op1 = NULL, *op2 = NULL, *op3 = NULL;

arch/powerpc/math-emu/math.c

28

#define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \

arch/powerpc/math-emu/math.c

333

op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);

arch/powerpc/math-emu/math.c

339

op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);

arch/powerpc/math-emu/math.c

345

op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);

arch/powerpc/math-emu/math.c

354

op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);

arch/powerpc/math-emu/math.c

364

op1 = (void *)(regs->gpr[idx] + sdisp);

arch/powerpc/math-emu/math.c

373

op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);

arch/powerpc/math-emu/math.c

378

op1 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);

arch/powerpc/math-emu/math.c

384

op1 = (void *)((idx ? regs->gpr[idx] : 0)

arch/powerpc/math-emu/math.c

393

op1 = (void *)(regs->gpr[idx]

arch/powerpc/math-emu/math.c

399

op1 = (void *)(long)((insn >> 23) & 0x7);

arch/powerpc/math-emu/math.c

406

op1 = (void *)(long)((insn >> 23) & 0x7);

arch/powerpc/math-emu/math.c

416

op1 = (void *)(long)((insn >> 12) & 0xf);

arch/powerpc/math-emu/math.c

421

op1 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);

arch/powerpc/math-emu/math.c

435

eflag = func(op0, op1, op2, op3);

arch/powerpc/math-emu/math.c

449

regs->gpr[idx] = (unsigned long)op1;

arch/s390/include/asm/percpu.h

58

#define arch_this_cpu_add(pcp, val, op1, op2, szcast) \

arch/s390/include/asm/percpu.h

74

op1 " %[old__],%[val__],%[ptr__]" \

arch/s390/net/bpf_jit_comp.c

217

#define _EMIT6(op1, op2) \

arch/s390/net/bpf_jit_comp.c

220

*(u32 *) (jit->prg_buf + jit->prg) = (op1); \

arch/s390/net/bpf_jit_comp.c

226

#define _EMIT6_DISP(op1, op2, disp) \

arch/s390/net/bpf_jit_comp.c

229

_EMIT6((op1) | __disp, op2); \

arch/s390/net/bpf_jit_comp.c

232

#define _EMIT6_DISP_LH(op1, op2, disp) \

arch/s390/net/bpf_jit_comp.c

237

_EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \

arch/s390/net/bpf_jit_comp.c

240

#define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \

arch/s390/net/bpf_jit_comp.c

242

_EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \

arch/s390/net/bpf_jit_comp.c

249

#define EMIT6_PCREL_RIEB(op1, op2, b1, b2, mask, target) \

arch/s390/net/bpf_jit_comp.c

252

_EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \

arch/s390/net/bpf_jit_comp.c

258

#define EMIT6_PCREL_RIEC(op1, op2, b1, imm, mask, target) \

arch/s390/net/bpf_jit_comp.c

261

_EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \

arch/s390/net/bpf_jit_comp.c

267

#define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \

arch/s390/net/bpf_jit_comp.c

270

_EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\

arch/sh/kernel/kprobes.c

144

struct kprobe *op1, *op2;

arch/sh/kernel/kprobes.c

148

op1 = this_cpu_ptr(&saved_next_opcode);

arch/sh/kernel/kprobes.c

153

op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr];

arch/sh/kernel/kprobes.c

156

op1->addr =

arch/sh/kernel/kprobes.c

161

op1->addr =

arch/sh/kernel/kprobes.c

166

op1->addr = (kprobe_opcode_t *) regs->pr;

arch/sh/kernel/kprobes.c

171

op1->addr = p->addr + 1;

arch/sh/kernel/kprobes.c

181

op1->addr = p->addr + 2;

arch/sh/kernel/kprobes.c

189

op1->addr = p->addr + 1;

arch/sh/kernel/kprobes.c

192

op1->opcode = *(op1->addr);

arch/sh/kernel/kprobes.c

193

arch_arm_kprobe(op1);

arch/x86/kernel/alternative.c

977

u8 op1, op2;

arch/x86/kernel/alternative.c

984

op1 = insn.opcode.bytes[0];

arch/x86/kernel/alternative.c

987

switch (op1) {

arch/x86/kvm/svm/svm_ops.h

19

#define svm_asm1(insn, op1, clobber...) \

arch/x86/kvm/svm/svm_ops.h

23

:: op1 : clobber : fault); \

arch/x86/kvm/svm/svm_ops.h

29

#define svm_asm2(insn, op1, op2, clobber...) \

arch/x86/kvm/svm/svm_ops.h

33

:: op1, op2 : clobber : fault); \

arch/x86/kvm/vmx/vmx_ops.h

191

#define vmx_asm1(insn, op1, error_args...) \

arch/x86/kvm/vmx/vmx_ops.h

197

: : op1 : "cc" : error, fault); \

arch/x86/kvm/vmx/vmx_ops.h

208

#define vmx_asm2(insn, op1, op2, error_args...) \

arch/x86/kvm/vmx/vmx_ops.h

214

: : op1, op2 : "cc" : error, fault); \

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

345

#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

348

#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

349

#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

350

#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

351

#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

357

#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

358

#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

58

#define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

59

REG_FIELD_PREP(GENMASK(19, 10), (op1)) | \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

62

#define __CS_ALU_INSTR(opcode, op1, op2) CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

63

CS_ALU_OPERAND_##op1, \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

67

#define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

68

#define CS_ALU_INSTR_LOADINV(op1, op2) __CS_ALU_INSTR(LOADINV, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

69

#define CS_ALU_INSTR_LOAD0(op1) __CS_ALU_INSTR(LOAD0, op1, NA)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

70

#define CS_ALU_INSTR_LOAD1(op1) __CS_ALU_INSTR(LOAD1, op1, NA)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

76

#define CS_ALU_INSTR_STORE(op1, op2) __CS_ALU_INSTR(STORE, op1, op2)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

77

#define CS_ALU_INSTR_STOREINV(op1, op2) __CS_ALU_INSTR(STOREINV, op1, op2)

drivers/gpu/host1x/cdma.c

138

static void host1x_pushbuffer_push(struct push_buffer *pb, u32 op1, u32 op2)

drivers/gpu/host1x/cdma.c

143

*(p++) = op1;

drivers/gpu/host1x/cdma.c

590

void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2)

drivers/gpu/host1x/cdma.c

597

op1, op2);

drivers/gpu/host1x/cdma.c

605

host1x_pushbuffer_push(pb, op1, op2);

drivers/gpu/host1x/cdma.c

617

void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,

drivers/gpu/host1x/cdma.c

626

trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2,

drivers/gpu/host1x/cdma.c

650

host1x_pushbuffer_push(pb, op1, op2);

drivers/gpu/host1x/cdma.h

83

void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);

drivers/gpu/host1x/cdma.h

84

void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,

drivers/gpu/host1x/hw/channel_hw.c

143

u32 op1 = host1x_opcode_gather_wide(g->words);

drivers/gpu/host1x/hw/channel_hw.c

146

host1x_cdma_push_wide(cdma, op1, op2, op3, op4);

drivers/gpu/host1x/hw/channel_hw.c

153

u32 op1 = host1x_opcode_gather(g->words);

drivers/gpu/host1x/hw/channel_hw.c

155

host1x_cdma_push(cdma, op1, op2);

drivers/iommu/msm_iommu.c

28

#define MRC(reg, processor, op1, crn, crm, op2) \

drivers/iommu/msm_iommu.c

30

" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

13

u16 qm_mulu16(u16 op1, u16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

15

return (u16) (((u32) op1 * (u32) op2) >> 16);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

26

s16 qm_muls16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

29

if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

32

result = ((s32) (op1) * (s32) (op2));

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

42

s32 qm_add32(s32 op1, s32 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

45

result = op1 + op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

46

if (op1 < 0 && op2 < 0 && result > 0)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

48

else if (op1 > 0 && op2 > 0 && result < 0)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

59

s16 qm_add16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

62

s32 temp = (s32) op1 + (s32) op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

78

s16 qm_sub16(s16 op1, s16 op2)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.c

81

s32 temp = (s32) op1 - (s32) op2;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

11

u16 qm_mulu16(u16 op1, u16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

13

s16 qm_muls16(s16 op1, s16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

15

s32 qm_add32(s32 op1, s32 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

17

s16 qm_add16(s16 op1, s16 op2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_qmath.h

19

s16 qm_sub16(s16 op1, s16 op2);

drivers/platform/x86/lenovo/ideapad-laptop.c

2042

unsigned long op1, op2;

drivers/platform/x86/lenovo/ideapad-laptop.c

2050

op1 = SBMC_CONSERVATION_OFF;

drivers/platform/x86/lenovo/ideapad-laptop.c

2054

op1 = SBMC_RAPID_CHARGE_OFF;

drivers/platform/x86/lenovo/ideapad-laptop.c

2058

op1 = SBMC_RAPID_CHARGE_OFF;

drivers/platform/x86/lenovo/ideapad-laptop.c

2069

err = exec_sbmc(priv->adev->handle, op1);

drivers/tty/serial/mpc52xx_uart.c

158

out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);

drivers/tty/serial/mpc52xx_uart.c

931

out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);

fs/smb/server/oplock.c

1038

static void copy_lease(struct oplock_info *op1, struct oplock_info *op2)

fs/smb/server/oplock.c

1040

struct lease *lease1 = op1->o_lease;

fs/smb/server/oplock.c

1043

op2->level = op1->level;

include/linux/pds/pds_adminq.h

1275

#define PDS_FWCTL_RPC_OPCODE_CMP(op1, op2) \

include/linux/pds/pds_adminq.h

1276

(PDS_FWCTL_RPC_OPCODE_GET_CMD(op1) == PDS_FWCTL_RPC_OPCODE_GET_CMD(op2) && \

include/linux/pds/pds_adminq.h

1277

PDS_FWCTL_RPC_OPCODE_GET_VER(op1) <= PDS_FWCTL_RPC_OPCODE_GET_VER(op2))

include/trace/events/host1x.h

50

TP_PROTO(const char *name, u32 op1, u32 op2),

include/trace/events/host1x.h

52

TP_ARGS(name, op1, op2),

include/trace/events/host1x.h

56

__field(u32, op1)

include/trace/events/host1x.h

62

__entry->op1 = op1;

include/trace/events/host1x.h

67

__entry->name, __entry->op1, __entry->op2)

include/trace/events/host1x.h

71

TP_PROTO(const char *name, u32 op1, u32 op2, u32 op3, u32 op4),

include/trace/events/host1x.h

73

TP_ARGS(name, op1, op2, op3, op4),

include/trace/events/host1x.h

77

__field(u32, op1)

include/trace/events/host1x.h

85

__entry->op1 = op1;

include/trace/events/host1x.h

92

__entry->name, __entry->op1, __entry->op2, __entry->op3,

lib/zlib_dfltcc/dfltcc_util.h

32

Byte **op1,

lib/zlib_dfltcc/dfltcc_util.h

39

Byte *t2 = op1 ? *op1 : NULL;

lib/zlib_dfltcc/dfltcc_util.h

90

if (op1)

lib/zlib_dfltcc/dfltcc_util.h

91

*op1 = t2;

lib/zstd/decompress/huf_decompress.c

1413

BYTE* op1 = ostart;

lib/zstd/decompress/huf_decompress.c

1433

HUF_DECODE_SYMBOLX2_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1434

HUF_DECODE_SYMBOLX2_1(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1435

HUF_DECODE_SYMBOLX2_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1436

HUF_DECODE_SYMBOLX2_0(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1454

HUF_DECODE_SYMBOLX2_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1458

HUF_DECODE_SYMBOLX2_1(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1462

HUF_DECODE_SYMBOLX2_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1466

HUF_DECODE_SYMBOLX2_0(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

1480

if (op1 > opStart2) return ERROR(corruption_detected);

lib/zstd/decompress/huf_decompress.c

1486

HUF_decodeStreamX2(op1, &bitD1, opStart2, dt, dtLog);

lib/zstd/decompress/huf_decompress.c

632

BYTE* op1 = ostart;

lib/zstd/decompress/huf_decompress.c

651

HUF_DECODE_SYMBOLX1_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

655

HUF_DECODE_SYMBOLX1_1(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

659

HUF_DECODE_SYMBOLX1_2(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

663

HUF_DECODE_SYMBOLX1_0(op1, &bitD1);

lib/zstd/decompress/huf_decompress.c

677

if (op1 > opStart2) return ERROR(corruption_detected);

lib/zstd/decompress/huf_decompress.c

683

HUF_decodeStreamX1(op1, &bitD1, opStart2, dt, dtLog);

scripts/gcc-plugins/gcc-common.h

315

static inline gimple gimple_build_assign_with_ops(enum tree_code subcode, tree lhs, tree op1, tree op2 MEM_STAT_DECL)

scripts/gcc-plugins/gcc-common.h

317

return gimple_build_assign(lhs, subcode, op1, op2 PASS_MEM_STAT);

scripts/gcc-plugins/latent_entropy_plugin.c

334

static gimple create_assign(enum tree_code code, tree lhs, tree op1,

scripts/gcc-plugins/latent_entropy_plugin.c

337

return gimple_build_assign_with_ops(code, lhs, op1, op2);

tools/arch/arm64/include/asm/esr.h

217

#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \

tools/arch/arm64/include/asm/esr.h

219

((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \

tools/arch/arm64/include/asm/esr.h

333

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

tools/arch/arm64/include/asm/esr.h

334

(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \

tools/arch/arm64/include/asm/esr.h

354

#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \

tools/arch/arm64/include/asm/esr.h

355

(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \

tools/arch/arm64/include/asm/sysreg.h

39

#define sys_reg(op0, op1, crn, crm, op2) \

tools/arch/arm64/include/asm/sysreg.h

40

(((op0) << Op0_shift) | ((op1) << Op1_shift) | \

tools/arch/arm64/include/asm/sysreg.h

91

#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)

tools/arch/arm64/include/uapi/asm/kvm.h

247

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \

tools/arch/arm64/include/uapi/asm/kvm.h

250

ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \

tools/arch/arm64/include/uapi/asm/kvm.h

545

#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \

tools/arch/arm64/include/uapi/asm/kvm.h

547

__u64 __op1 = (op1) & 3; \

tools/objtool/arch/x86/decode.c

225

unsigned char op1, op2, op3, prefix,

tools/objtool/arch/x86/decode.c

252

op1 = ins.opcode.bytes[0];

tools/objtool/arch/x86/decode.c

278

switch (op1) {

tools/objtool/arch/x86/decode.c

299

op->src.reg = (op1 & 0x7) + 8*rex_b;

tools/objtool/arch/x86/decode.c

311

op->dest.reg = (op1 & 0x7) + 8*rex_b;

tools/objtool/arch/x86/decode.c

351

if (op1 & 2) { /* sign extend */

tools/objtool/arch/x86/decode.c

352

if (op1 & 1) { /* imm32 */

tools/testing/selftests/kvm/arm64/get-reg-list.c

214

unsigned op0, op1, crn, crm, op2;

tools/testing/selftests/kvm/arm64/get-reg-list.c

265

op1 = (id & KVM_REG_ARM64_SYSREG_OP1_MASK) >> KVM_REG_ARM64_SYSREG_OP1_SHIFT;

tools/testing/selftests/kvm/arm64/get-reg-list.c

269

TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2),

tools/testing/selftests/kvm/arm64/get-reg-list.c

271

printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2);