nvjpg
NVKM_LAYOUT_INST(NVKM_ENGINE_NVJPG , struct nvkm_engine , nvjpg, 8)
if (WARN_ON(inst >= ARRAY_SIZE(device->nvjpg)))
return nvkm_rm_engine_new_(rm, type, inst, gpu->nvjpg.class, &device->nvjpg[inst]);
ret = rm->api->nvjpg->alloc(chan, handle, class, inst, &obj->rm);
.nvjpg.class = NVCDD1_VIDEO_NVJPG,
.nvjpg.class = NVCFD1_VIDEO_NVJPG,
.nvjpg.class = NVB8D1_VIDEO_NVJPG,
} nvjpg;
struct nvkm_gsp_object *nvjpg)
args = nvkm_gsp_rm_alloc_get(chan, handle, class, sizeof(*args), nvjpg);
return nvkm_gsp_rm_alloc_wr(nvjpg, args);
.nvjpg = &r535_nvjpg,
.nvjpg = &r535_nvjpg,
} *ce, *nvdec, *nvenc, *nvjpg, *ofa;
static int nvjpg_load_falcon_firmware(struct nvjpg *nvjpg)
struct host1x_client *client = &nvjpg->client.base;
struct tegra_drm *tegra = nvjpg->client.drm;
if (nvjpg->falcon.firmware.virt)
err = falcon_read_firmware(&nvjpg->falcon, nvjpg->config->firmware);
size = nvjpg->falcon.firmware.size;
virt = dma_alloc_coherent(nvjpg->dev, size, &iova, GFP_KERNEL);
nvjpg->falcon.firmware.virt = virt;
nvjpg->falcon.firmware.iova = iova;
err = falcon_load_firmware(&nvjpg->falcon);
phys = dma_map_single(nvjpg->dev, virt, size, DMA_TO_DEVICE);
err = dma_mapping_error(nvjpg->dev, phys);
nvjpg->falcon.firmware.phys = phys;
dma_free_coherent(nvjpg->dev, size, virt, iova);
struct nvjpg *nvjpg = dev_get_drvdata(dev);
err = clk_prepare_enable(nvjpg->clk);
err = nvjpg_load_falcon_firmware(nvjpg);
err = falcon_boot(&nvjpg->falcon);
clk_disable_unprepare(nvjpg->clk);
struct nvjpg *nvjpg = dev_get_drvdata(dev);
clk_disable_unprepare(nvjpg->clk);
struct nvjpg *nvjpg;
nvjpg = devm_kzalloc(dev, sizeof(*nvjpg), GFP_KERNEL);
if (!nvjpg)
nvjpg->config = of_device_get_match_data(dev);
nvjpg->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(nvjpg->regs))
return PTR_ERR(nvjpg->regs);
nvjpg->clk = devm_clk_get(dev, "nvjpg");
if (IS_ERR(nvjpg->clk)) {
return PTR_ERR(nvjpg->clk);
err = clk_set_rate(nvjpg->clk, ULONG_MAX);
nvjpg->falcon.dev = dev;
nvjpg->falcon.regs = nvjpg->regs;
err = falcon_init(&nvjpg->falcon);
platform_set_drvdata(pdev, nvjpg);
INIT_LIST_HEAD(&nvjpg->client.base.list);
nvjpg->client.base.ops = &nvjpg_client_ops;
nvjpg->client.base.dev = dev;
nvjpg->client.base.class = HOST1X_CLASS_NVJPG;
nvjpg->dev = dev;
INIT_LIST_HEAD(&nvjpg->client.list);
nvjpg->client.version = nvjpg->config->version;
nvjpg->client.ops = &nvjpg_ops;
err = host1x_client_register(&nvjpg->client.base);
falcon_exit(&nvjpg->falcon);
struct nvjpg *nvjpg = platform_get_drvdata(pdev);
host1x_client_unregister(&nvjpg->client.base);
falcon_exit(&nvjpg->falcon);
static inline struct nvjpg *to_nvjpg(struct tegra_drm_client *client)
return container_of(client, struct nvjpg, client);
struct nvjpg *nvjpg = to_nvjpg(drm);
dev_err(nvjpg->dev, "failed to attach to domain: %d\n", err);
struct nvjpg *nvjpg = to_nvjpg(drm);
dma_unmap_single(nvjpg->dev, nvjpg->falcon.firmware.phys,
nvjpg->falcon.firmware.size, DMA_TO_DEVICE);
tegra_drm_free(tegra, nvjpg->falcon.firmware.size,
nvjpg->falcon.firmware.virt,
nvjpg->falcon.firmware.iova);
dma_free_coherent(nvjpg->dev, nvjpg->falcon.firmware.size,
nvjpg->falcon.firmware.virt,
nvjpg->falcon.firmware.iova);