omap_writel
omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
omap_writel(val, OMAP_IH1_BASE + offset);
omap_writel(l, EMIFS_CCS(1));
omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */
omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */
omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3));
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, MOD_CONF_CTRL_1);
omap_writel(omap_readl(MOD_CONF_CTRL_0) |
omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
omap_writel(l, EMIFS_CONFIG);
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
EXPORT_SYMBOL(omap_writel);
omap_writel(reg, cfg->mux_reg);
omap_writel(pu_pd, cfg->pu_pd_reg);
omap_writel(pull, cfg->pull_reg);
omap_writel(val, OCPI_PROT);
omap_writel(val, OCPI_SEC);
omap_writel(l, reg);
omap_writel(l, reg);
omap_writel(use_idlect1, ARM_IDLECT1);
omap_writel(saved_idlect1, ARM_IDLECT1);
omap_writel(~level1_wake, OMAP_IH1_MIR);
omap_writel(~level2_wake, OMAP_IH2_MIR);
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
omap_writel(~0x0, OMAP_IH2_2_MIR);
omap_writel(~0x0, OMAP_IH2_3_MIR);
omap_writel(1, OMAP_IH2_CONTROL);
omap_writel(1, OMAP_IH1_CONTROL);
omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
omap_writel(l, MOD_CONF_CTRL_1);
omap_writel(syscon, OTG_SYSCON_1);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel(l, USB_TRANSCEIVER_CTRL);
omap_writel((1 << 1) | (1 << 0), OMAP1510_LB_MMU_CTL);
omap_writel(0, OMAP1510_LB_MMU_CTL);
omap_writel((omap_readl(OMAP1510_LB_CLOCK_DIV) & 0xfffffff8) | 0x4,
omap_writel((lbaddr & 0x0fffffff) >> 22, OMAP1510_LB_MMU_CAM_H);
omap_writel(((lbaddr & 0x003ffc00) >> 6) | 0xc,
omap_writel(physaddr >> 16, OMAP1510_LB_MMU_RAM_H);
omap_writel((physaddr & 0x0000fc00) | 0x300, OMAP1510_LB_MMU_RAM_L);
omap_writel(tlb << 4, OMAP1510_LB_MMU_LCK);
omap_writel(0x1, OMAP1510_LB_MMU_LD_TLB);
omap_writel(omap_readl(OMAP1510_LB_MMU_CTL) | (1 << 3), OMAP1510_LB_MMU_CTL);
omap_writel(val, MOD_CONF_CTRL_0);
omap_writel(syscon, OTG_SYSCON_1);
omap_writel(syscon, OTG_SYSCON_2);
omap_writel(l, OTG_CTRL);
omap_writel(l, OTG_CTRL);
omap_writel(l, FUNC_MUX_CTRL_0);
omap_writel(l, OTG_CTRL);
omap_writel(tmp, FUNC_MUX_CTRL_0);
omap_writel(tmp, FUNC_MUX_CTRL_0);
omap_writel(l, OTG_CTRL);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(status, OMAP_LCDC_STATUS);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(l, OMAP_LCDC_TIMING2);
omap_writel(l, OMAP_LCDC_TIMING0);
omap_writel(l, OMAP_LCDC_TIMING1);
omap_writel(l, OMAP_LCDC_TIMING2);
omap_writel(l, OMAP_LCDC_CONTROL);
omap_writel(l, MOD_CONF_CTRL_1);
omap_writel(l, MOD_CONF_CTRL_1);
omap_writel(l, ARM_IDLECT2);
extern void omap_writel(u32 v, u32 pa);