arch/mips/kernel/perf_event_mipsxx.c

1000

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1001

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1018

[C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1022

[C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1028

[C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1032

[C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1044

[C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1048

[C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1055

[C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1059

[C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1065

[C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1069

[C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1076

[C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1080

[C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1098

[C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1099

[C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1102

[C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1103

[C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1109

[C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1113

[C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1125

[C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1129

[C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1141

[C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1145

[C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1152

[C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1156

[C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1167

[C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1168

[C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1171

[C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1172

[C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1177

[C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1178

[C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1184

[C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1185

[C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1188

[C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1189

[C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1195

[C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1196

[C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1213

[C(RESULT_MISS)] = { 0x04, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1216

[C(RESULT_MISS)] = { 0x04, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1229

[C(RESULT_MISS)] = { 0x09, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1232

[C(RESULT_MISS)] = { 0x09, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1237

[C(RESULT_MISS)] = { 0x0c, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1240

[C(RESULT_MISS)] = { 0x0c, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1247

[C(RESULT_MISS)] = { 0x01, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1251

[C(RESULT_MISS)] = { 0x01, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1385

[C(RESULT_MISS)] = { 12, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1389

[C(RESULT_MISS)] = { 12, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1395

[C(RESULT_MISS)] = { 10, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1399

[C(RESULT_MISS)] = { 10, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1412

[C(RESULT_MISS)] = { 28, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1416

[C(RESULT_MISS)] = { 28, CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

1422

[C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1425

[C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1713

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1716

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1727

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1730

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1743

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1746

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1753

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1756

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1767

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1770

raw_id > 255 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1779

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1783

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1786

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1798

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1801

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1813

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1816

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1824

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

938

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

939

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

941

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

947

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

948

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

950

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

954

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

955

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

957

[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

958

[PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

959

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

960

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

965

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

967

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

999

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },