arch/mips/kernel/perf_event_mipsxx.c

1000

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1017

[C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1018

[C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1021

[C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1022

[C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

1027

[C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1031

[C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1035

[C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1045

[C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1049

[C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1054

[C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1058

[C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1064

[C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1068

[C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1075

[C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1079

[C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1108

[C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1112

[C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1116

[C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1126

[C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1130

[C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1140

[C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1144

[C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1151

[C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1155

[C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1167

[C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1168

[C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1171

[C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1172

[C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1177

[C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1178

[C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1184

[C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1185

[C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1188

[C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1189

[C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1195

[C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1196

[C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

1221

[C(RESULT_MISS)] = { 0x04, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

1224

[C(RESULT_MISS)] = { 0x04, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

1246

[C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

1250

[C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

1384

[C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1388

[C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1394

[C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1398

[C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1402

[C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

1411

[C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1415

[C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },

arch/mips/kernel/perf_event_mipsxx.c

1713

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1716

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1727

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1730

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1743

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1746

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1753

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1756

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1767

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1770

raw_id > 255 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1779

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1783

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1786

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1798

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1801

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1813

raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

arch/mips/kernel/perf_event_mipsxx.c

1816

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

1824

raw_id > 127 ? CNTR_ODD : CNTR_EVEN;

arch/mips/kernel/perf_event_mipsxx.c

938

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

939

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

940

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

947

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },

arch/mips/kernel/perf_event_mipsxx.c

948

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },

arch/mips/kernel/perf_event_mipsxx.c

949

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },

arch/mips/kernel/perf_event_mipsxx.c

954

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

955

[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

957

[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

958

[PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

959

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

960

[PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },

arch/mips/kernel/perf_event_mipsxx.c

964

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

966

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },

arch/mips/kernel/perf_event_mipsxx.c

999

[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },