omap_ctrl_readl
u32 emu0 = omap_ctrl_readl(AM335X_PIN_EMU0);
u32 emu1 = omap_ctrl_readl(AM335X_PIN_EMU1);
val = omap_ctrl_readl(offset);
val = omap_ctrl_readl(offset);
tmp = omap_ctrl_readl(offset);
tmp = omap_ctrl_readl(offset);
control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
omap_ctrl_readl(am43xx_control_reg_offsets[i]);
extern u32 omap_ctrl_readl(u16 offset);
status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);