drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

124

nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz,

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

148

struct nv40_clk *clk = nv40_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

188

struct nv40_clk *clk = nv40_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

205

nv40_clk = {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

224

struct nv40_clk *clk;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

232

return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

24

#define nv40_clk(p) container_of((p), struct nv40_clk, base)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

40

read_pll_1(struct nv40_clk *clk, u32 reg)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

56

read_pll_2(struct nv40_clk *clk, u32 reg)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

82

read_clk(struct nv40_clk *clk, u32 src)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

99

struct nv40_clk *clk = nv40_clk(base);