CNTR_ALL
[C(RESULT_ACCESS)] = { 0x156, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x155, CNTR_ALL },
[C(RESULT_MISS)] = { 0x153, CNTR_ALL },
[C(RESULT_MISS)] = { 0x18, CNTR_ALL },
[C(RESULT_MISS)] = { 0x18, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x1b6, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x1b7, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x1bf, CNTR_ALL },
[C(RESULT_MISS)] = { 0x92, CNTR_ALL },
[C(RESULT_MISS)] = { 0x92, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x94, CNTR_ALL },
[C(RESULT_MISS)] = { 0x9c, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x1e, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1f, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0xaa, CNTR_ALL },
[C(RESULT_MISS)] = { 0xa9, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x1c, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1d, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x2e, CNTR_ALL },
[C(RESULT_MISS)] = { 0x2f, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x14, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1b, CNTR_ALL },
[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x02, CNTR_ALL },
[C(RESULT_MISS)] = { 0x08, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
[C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
[C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
[C(RESULT_MISS)] = { 0x35, CNTR_ALL },
[C(RESULT_MISS)] = { 0x35, CNTR_ALL },
[C(RESULT_MISS)] = { 0x37, CNTR_ALL },
raw_event.cntr_mask = CNTR_ALL;
raw_event.cntr_mask = CNTR_ALL;
raw_event.cntr_mask = CNTR_ALL;
[PERF_COUNT_HW_CPU_CYCLES] = { 0x80, CNTR_ALL },
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x81, CNTR_ALL },
[PERF_COUNT_HW_CACHE_MISSES] = { 0x18, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x94, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x9c, CNTR_ALL },
[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_ALL },
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_ALL },
[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x1c, CNTR_ALL },
[PERF_COUNT_HW_CACHE_MISSES] = { 0x1d, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x08, CNTR_ALL },
[PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
[PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
[PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },