drivers/gpu/drm/nouveau/dispnv04/crtc.c

1076

struct nv04_display *disp = container_of(event, typeof(*disp), flip);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

1150

struct nv04_display *dispnv04 = nv04_display(dev);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

124

struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

241

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

466

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

467

struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

546

regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

612

struct nv04_display *disp = nv04_display(crtc->dev);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

665

NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

67

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

675

struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

677

struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

697

uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

702

nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

737

nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

755

struct nv04_display *disp = nv04_display(crtc->dev);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

786

rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

797

nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

803

struct nv04_display *disp = nv04_display(crtc->dev);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

82

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

845

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/cursor.c

42

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/dac.c

432

uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];

drivers/gpu/drm/nouveau/dispnv04/dac.c

457

(nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));

drivers/gpu/drm/nouveau/dispnv04/dfp.c

122

fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

137

fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

207

struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

237

if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {

drivers/gpu/drm/nouveau/dispnv04/dfp.c

238

int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

251

struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

288

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/dfp.c

289

struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/dfp.c

464

nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =

drivers/gpu/drm/nouveau/dispnv04/dfp.c

557

nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);

drivers/gpu/drm/nouveau/dispnv04/dfp.c

558

nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

560

NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);

drivers/gpu/drm/nouveau/dispnv04/dfp.c

606

(&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);

drivers/gpu/drm/nouveau/dispnv04/dfp.c

95

struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;

drivers/gpu/drm/nouveau/dispnv04/disp.c

101

struct nv04_display *disp = nv04_display(dev);

drivers/gpu/drm/nouveau/dispnv04/disp.c

191

struct nv04_display *disp = nv04_display(dev);

drivers/gpu/drm/nouveau/dispnv04/disp.c

220

struct nv04_display *disp;

drivers/gpu/drm/nouveau/dispnv04/disp.c

60

struct nv04_display *disp = nv04_display(dev);

drivers/gpu/drm/nouveau/dispnv04/disp.h

93

static inline struct nv04_display *

drivers/gpu/drm/nouveau/dispnv04/hw.c

299

nv04_display(dev)->saved_vga_font[plane][i] =

drivers/gpu/drm/nouveau/dispnv04/hw.c

302

iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],

drivers/gpu/drm/nouveau/dispnv04/hw.h

376

&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];

drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c

546

struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

107

struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

146

struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

79

struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;

drivers/gpu/drm/nouveau/dispnv04/tvnv17.c

410

uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[

drivers/gpu/drm/nouveau/dispnv04/tvnv17.c

471

struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];