drivers/clk/ti/clock.h

268

int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/ti/dpll.c

28

.set_rate = &omap3_noncore_dpll_set_rate,

drivers/clk/ti/dpll.c

50

.set_rate = &omap3_noncore_dpll_set_rate,

drivers/clk/ti/dpll.c

62

.set_rate = &omap3_noncore_dpll_set_rate,

drivers/clk/ti/dpll.c

99

.set_rate = &omap3_noncore_dpll_set_rate,

drivers/clk/ti/dpll3xxx.c

1026

return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);

drivers/clk/ti/dpll3xxx.c

1117

return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);

drivers/clk/ti/dpll3xxx.c

716

ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);