nsp32_write2
nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
nsp32_write2(base, TRANSFER_CONTROL, 0);
nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
nsp32_write2(base, TIMER_SET, TIMER_STOP);
nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
nsp32_write2(base, IRQ_CONTROL, 0);
nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
nsp32_write2(base, TIMER_SET, TIMER_STOP);
nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
nsp32_write2(base, IRQ_CONTROL, 0);
nsp32_write2(base, TRANSFER_CONTROL, 0);
nsp32_write2(base, TRANSFER_CONTROL, 0);
nsp32_write2(base, COMMAND_CONTROL,
nsp32_write2(base, TRANSFER_CONTROL, transfer);
nsp32_write2(base, COMMAND_CONTROL, command);
nsp32_write2(base, TRANSFER_CONTROL, 0);
nsp32_write2(base, BM_CNT, 0);
nsp32_write2(base, TRANSFER_CONTROL, 0);
nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
nsp32_write2(base, IRQ_CONTROL, 0);
nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
nsp32_write2(base, COMMAND_CONTROL,
nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
nsp32_write2(base, TRANSFER_CONTROL, command);
nsp32_write2(base, COMMAND_CONTROL, command);
nsp32_write2(base, IRQ_CONTROL, 0);