o2
clr %o0; clr %o1; clr %o2; clr %o3; \
#define r_X %o2
o2(); t2(4); t2(1);
u32 o1, o2;
o2 = o1;
} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
int i, m1, m2, m3, o1, o2;
o2 = (size + (size / 4)) % PAGE_SIZE;
size, m1, m2, m3, o1, o2);
o2 = (size + (size / 2)) % PAGE_SIZE;
size, m1, m2, m3, o1, o2);
pt3->offset = pt1->offset + o2;
SDHCI_PCI_DEVICE(O2, 8120, o2),
SDHCI_PCI_DEVICE(O2, 8220, o2),
SDHCI_PCI_DEVICE(O2, 8221, o2),
SDHCI_PCI_DEVICE(O2, 8320, o2),
SDHCI_PCI_DEVICE(O2, 8321, o2),
SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
SDHCI_PCI_DEVICE(O2, SDS0, o2),
SDHCI_PCI_DEVICE(O2, SDS1, o2),
SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
SDHCI_PCI_DEVICE(O2, GG8_9860, o2),
SDHCI_PCI_DEVICE(O2, GG8_9861, o2),
SDHCI_PCI_DEVICE(O2, GG8_9862, o2),
SDHCI_PCI_DEVICE(O2, GG8_9863, o2),
#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \
o2, \
struct nfs41_server_owner *o2);
struct nfs41_server_owner *o2)
if (o1->major_id_sz != o2->major_id_sz)
return memcmp(o1->major_id, o2->major_id, o1->major_id_sz) == 0;
compare_blob(const struct xdr_netobj *o1, const struct xdr_netobj *o2)
if (o1->len < o2->len)
if (o1->len > o2->len)
return memcmp(o1->data, o2->data, o1->len);
u64 o2 = t3 << 25 | t2 >> 26;
put_unaligned_le64(o2, b2);
u64 o2;
o2 = f2_;
b[2U] = o2;
I_WW(t); I_WW(t2); I_WW(o.base); I_WW(o2.base); I_WW(o3.base);
ww_mutex_init(&o, &ww_lockdep); ww_mutex_init(&o2, &ww_lockdep); ww_mutex_init(&o3, &ww_lockdep);
ww_mutex_base_lock(&o2.base);
o2.ctx = &t2;
mutex_release(&o2.base.dep_map, _THIS_IP_);
ret = WWL(&o2, &t);
o2.ctx = NULL;
mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);
ww_mutex_base_unlock(&o2.base);
WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
o2.ctx = NULL;
mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);
ww_mutex_base_unlock(&o2.base);
ww_mutex_lock_slow(&o2, &t);
ww_mutex_base_lock(&o2.base);
o2.ctx = &t2;
mutex_release(&o2.base.dep_map, _THIS_IP_);
ret = WWL(&o2, &t);
o2.ctx = NULL;
mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);
ww_mutex_base_unlock(&o2.base);
WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
o2.ctx = NULL;
mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);
ww_mutex_base_unlock(&o2.base);
ww_mutex_lock_slow(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
WWU(&o2);
ww_mutex_base_lock(&o2.base);
mutex_release(&o2.base.dep_map, _THIS_IP_);
o2.ctx = &t2;
ret = WWL(&o2, &t);
WWU(&o2);
WWL1(&o2);
ret = WWT(&o2);
WWU(&o2);
ret = WWL(&o2, &t);
WWU(&o2);
WWL1(&o2);
WWU(&o2);
ret = WWT(&o2);
WWU(&o2);
ret = WWL(&o2, &t);
WWL1(&o2);
ret = WWT(&o2);
ret = WWL(&o2, &t);
static struct ww_mutex o, o2, o3;
#define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
{R_PLL2ODIV, o2}, \