nxp_c45_macsec_write
ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN |
ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL,
ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN);
ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD);
ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE);
ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP);
ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK);
ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN);
nxp_c45_macsec_write(phydev, MACSEC_EVR,
nxp_c45_macsec_write(phydev, MACSEC_EVER, reg);
nxp_c45_macsec_write(phydev, sa_regs->npn, npn.lower);
nxp_c45_macsec_write(phydev, sa_regs->xnpn, npn.upper);
nxp_c45_macsec_write(phydev, sa_regs->lnpn, lnpn.lower);
nxp_c45_macsec_write(phydev, sa_regs->lxnpn, lnpn.upper);
nxp_c45_macsec_write(phydev, reg, value);
nxp_c45_macsec_write(phydev, reg, value);
nxp_c45_macsec_write(phydev, sa_regs->ssci, value);
nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A);
nxp_c45_macsec_write(phydev, sa->regs->ipis, 0);
nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0);
nxp_c45_macsec_write(phydev, sa->regs->ipos, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0);
nxp_c45_macsec_write(phydev, sa->regs->opps, 0);
nxp_c45_macsec_write(phydev, sa->regs->opes, 0);
nxp_c45_macsec_write(phydev, sa_regs->cs, cfg);
nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
nxp_c45_macsec_write(phydev, sci_base_addr, lsci >> 32);
nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci);
nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id);
nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id);
nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id);
nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id);
nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg);
nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg);
nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0);
nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0);
nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);
nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg);
nxp_c45_macsec_write(phydev, MACSEC_RPW,
nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg);
nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0);
nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0);
nxp_c45_macsec_write(phydev, MACSEC_RPW, 0);
nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0);
nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0);
nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0);
nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);