drivers/gpu/drm/bridge/nwl-dsi.c

221

nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);

drivers/gpu/drm/bridge/nwl-dsi.c

224

nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);

drivers/gpu/drm/bridge/nwl-dsi.c

225

nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);

drivers/gpu/drm/bridge/nwl-dsi.c

227

nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);

drivers/gpu/drm/bridge/nwl-dsi.c

228

nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);

drivers/gpu/drm/bridge/nwl-dsi.c

234

nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);

drivers/gpu/drm/bridge/nwl-dsi.c

239

nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);

drivers/gpu/drm/bridge/nwl-dsi.c

242

nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);

drivers/gpu/drm/bridge/nwl-dsi.c

244

nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);

drivers/gpu/drm/bridge/nwl-dsi.c

245

nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);

drivers/gpu/drm/bridge/nwl-dsi.c

246

nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);

drivers/gpu/drm/bridge/nwl-dsi.c

247

nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);

drivers/gpu/drm/bridge/nwl-dsi.c

251

nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);

drivers/gpu/drm/bridge/nwl-dsi.c

290

nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);

drivers/gpu/drm/bridge/nwl-dsi.c

291

nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);

drivers/gpu/drm/bridge/nwl-dsi.c

292

nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,

drivers/gpu/drm/bridge/nwl-dsi.c

296

nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,

drivers/gpu/drm/bridge/nwl-dsi.c

305

nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);

drivers/gpu/drm/bridge/nwl-dsi.c

306

nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);

drivers/gpu/drm/bridge/nwl-dsi.c

311

nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);

drivers/gpu/drm/bridge/nwl-dsi.c

312

nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,

drivers/gpu/drm/bridge/nwl-dsi.c

316

nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);

drivers/gpu/drm/bridge/nwl-dsi.c

317

nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);

drivers/gpu/drm/bridge/nwl-dsi.c

318

nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);

drivers/gpu/drm/bridge/nwl-dsi.c

320

nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);

drivers/gpu/drm/bridge/nwl-dsi.c

321

nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);

drivers/gpu/drm/bridge/nwl-dsi.c

322

nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);

drivers/gpu/drm/bridge/nwl-dsi.c

323

nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);

drivers/gpu/drm/bridge/nwl-dsi.c

325

nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);

drivers/gpu/drm/bridge/nwl-dsi.c

326

nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);

drivers/gpu/drm/bridge/nwl-dsi.c

327

nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);

drivers/gpu/drm/bridge/nwl-dsi.c

328

nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);

drivers/gpu/drm/bridge/nwl-dsi.c

340

nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);

drivers/gpu/drm/bridge/nwl-dsi.c

341

nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);

drivers/gpu/drm/bridge/nwl-dsi.c

520

nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);

drivers/gpu/drm/bridge/nwl-dsi.c

536

nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);

drivers/gpu/drm/bridge/nwl-dsi.c

559

nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);

drivers/gpu/drm/bridge/nwl-dsi.c

562

nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);