drivers/pci/controller/pcie-xilinx-nwl.c

311

nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);

drivers/pci/controller/pcie-xilinx-nwl.c

343

nwl_bridge_writel(pcie, 1 << bit, status_reg);

drivers/pci/controller/pcie-xilinx-nwl.c

379

nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

393

nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

631

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |

drivers/pci/controller/pcie-xilinx-nwl.c

635

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |

drivers/pci/controller/pcie-xilinx-nwl.c

640

nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);

drivers/pci/controller/pcie-xilinx-nwl.c

641

nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);

drivers/pci/controller/pcie-xilinx-nwl.c

647

nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);

drivers/pci/controller/pcie-xilinx-nwl.c

649

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &

drivers/pci/controller/pcie-xilinx-nwl.c

652

nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);

drivers/pci/controller/pcie-xilinx-nwl.c

658

nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);

drivers/pci/controller/pcie-xilinx-nwl.c

660

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &

drivers/pci/controller/pcie-xilinx-nwl.c

663

nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);

drivers/pci/controller/pcie-xilinx-nwl.c

682

nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),

drivers/pci/controller/pcie-xilinx-nwl.c

684

nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),

drivers/pci/controller/pcie-xilinx-nwl.c

688

nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,

drivers/pci/controller/pcie-xilinx-nwl.c

692

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |

drivers/pci/controller/pcie-xilinx-nwl.c

696

nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);

drivers/pci/controller/pcie-xilinx-nwl.c

699

nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,

drivers/pci/controller/pcie-xilinx-nwl.c

704

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |

drivers/pci/controller/pcie-xilinx-nwl.c

718

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |

drivers/pci/controller/pcie-xilinx-nwl.c

724

nwl_bridge_writel(pcie, ecam_val, E_ECAM_CONTROL);

drivers/pci/controller/pcie-xilinx-nwl.c

726

nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),

drivers/pci/controller/pcie-xilinx-nwl.c

728

nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),

drivers/pci/controller/pcie-xilinx-nwl.c

751

nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

754

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &

drivers/pci/controller/pcie-xilinx-nwl.c

758

nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

761

nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

764

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &

drivers/pci/controller/pcie-xilinx-nwl.c

768

nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);

drivers/pci/controller/pcie-xilinx-nwl.c

771

nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |