nvkm_memory_addr
gpuobj->addr = nvkm_memory_addr(gpuobj->memory);
(*pgpuobj)->addr = nvkm_memory_addr(memory);
chan->push |= nvkm_memory_addr(chan->memory) >> 8;
u64 addr = nvkm_memory_addr(falcon->core);
u64 addr = nvkm_memory_addr(memory) + start;
u64 addr = nvkm_memory_addr(memory) + start;
const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
u64 addr = nvkm_memory_addr(memory) + start;
const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
const u64 user = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 |
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
nvkm_memory_addr(ramfc)) >> 16) |
u64 addr = nvkm_memory_addr(memory) + start;
u64 addr = nvkm_memory_addr(memory) + start;
args->v0.inst = nvkm_memory_addr(chan->inst->memory);
nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
u32 inst = nvkm_memory_addr(chan->inst);
nvkm_memory_addr(gr->ctxtab) >> 4);
u32 inst = nvkm_memory_addr(chan->inst);
nvkm_memory_addr(gr->ctxtab) >> 4);
addr = nvkm_memory_addr(xtensa->gpu_fw);
falcon->func->bind_inst(falcon, target, nvkm_memory_addr(fw->inst));
acr->wpr_start = nvkm_memory_addr(acr->wpr);
desc->ucode_blob_base = nvkm_memory_addr(acr->wpr);
acr->shadow_start = nvkm_memory_addr(acr->wpr);
const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12;
u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12;
const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
return nvkm_memory_addr(buffer->mem);
nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->base.mmu_wr) >> 8);
nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->base.mmu_rd) >> 8);
addr = nvkm_memory_addr(ram->ltrain.memory);
vmm->pd->pt[0]->addr = nvkm_memory_addr(vmm->pd->pt[0]->memory);
ctrl->physicalAddr = nvkm_memory_addr(memory);
ctrl->instMemPhysAddr = nvkm_memory_addr(disp->inst->memory);
return fbsr_vram(fbsr, type, nvkm_memory_addr(memory), nvkm_memory_size(memory));
nvkm_memory_addr(chan->userd.mem) + chan->userd.base,
entry->gpuPhysAddr = nvkm_memory_addr(pmem[i]);
nvkm_memory_addr(golden.inst),
nvkm_memory_addr(golden.inst) + 0x1000,
nvkm_memory_addr(golden.inst) + 0x2000,
ctrl->physicalAddr = nvkm_memory_addr(memory);
nvkm_memory_addr(gr->scrubber.inst),
nvkm_memory_addr(gr->scrubber.inst) + 0x1000,
nvkm_memory_addr(gr->scrubber.inst) + 0x2000,
zero, nvkm_memory_addr(memory), nvkm_memory_size(memory));
nvkm_memory_addr(&eobj->base.memory),
return nvkm_memory_addr(nv50_instobj(memory)->ram);
u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL;
u64 addr = (nvkm_memory_addr(iobj->ram) + offset) & 0x000000fffffULL;
u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL;
u64 addr = (nvkm_memory_addr(iobj->ram) + offset) & 0x000000fffffULL;
u64 tag_base = nvkm_memory_addr(ltc->tag_ram) + tag_margin;
pt->addr = nvkm_memory_addr(pt->memory);
const u64 addr = nvkm_memory_addr(memory);
addr -= ((nvkm_memory_addr(pt) >> 19) + 1) << 19;
args->v0.addr = nvkm_memory_addr(umem->memory);