drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.h

32

int nvkm_disp_chan_new(const struct nvkm_oclass *, void *, u32, struct nvkm_object **);

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

335

{{0,0,G82_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

336

{{0,0,G82_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

337

{{0,0,G82_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

339

{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

365

{{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

366

{{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

367

{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

369

{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &gt200_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c

139

{{ 0, 0,GA102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

1247

{{0,0,GF110_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

1248

{{0,0,GF110_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

1249

{{0,0,GF110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

1251

{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gf119_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

319

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

320

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

321

{{0,0,GK104_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

323

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

45

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

46

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

47

{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

49

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

100

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

101

{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

103

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

99

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

182

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

183

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

184

{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

186

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c

71

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c

72

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c

73

{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c

75

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

186

{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gp102_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

187

{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gp102_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

188

{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gp102_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c

190

{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gp102_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c

95

{{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c

96

{{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c

97

{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c

99

{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &gt200_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

253

{{0,0,GT214_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

254

{{0,0,GT214_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

255

{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

257

{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

1241

{{ 0, 0,GV100_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c

59

{{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c

60

{{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c

61

{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c

63

{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &gt200_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c

73

{{0,0,GT214_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c

74

{{0,0,GT214_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c

75

{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c

77

{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1781

{{0,0,NV50_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs },

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1782

{{0,0,NV50_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm },

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1783

{{0,0,NV50_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &nv50_disp_base },

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1785

{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &nv50_disp_ovly },

drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c

225

{{ 0, 0,TU102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

1767

rm->user[4].ctor = nvkm_disp_chan_new;