drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h

120

int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);

drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c

120

lo = max(nvkm_clk_read(clk, domain->name), 0);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c

601

ret = nvkm_clk_read(clk, clock->name);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

184

return nvkm_clk_read(&clk->base, nv_clk_src_mpll);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

185

return nvkm_clk_read(&clk->base, nv_clk_src_mdiv);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

54

return nvkm_clk_read(&clk->base, nv_clk_src_sppll0);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

55

return nvkm_clk_read(&clk->base, nv_clk_src_sppll1);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

79

sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

82

sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c

214

*freq = nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c

285

nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

602

cur_freq = nvkm_clk_read(&clk->base.base, nv_clk_src_gpc);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

100

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

102

case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

103

case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

110

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

112

case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

118

return nvkm_clk_read(&clk->base, nv_clk_src_core);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

121

return nvkm_clk_read(&clk->base, nv_clk_src_core);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

124

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

125

case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

126

case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

134

return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

135

return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

148

return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

174

pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

212

if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4))

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

213

out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

239

if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

54

u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

95

return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

97

return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

103

case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

104

case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

145

return nvkm_clk_read(&clk->base, nv_clk_src_crystal);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

152

return nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

171

return nvkm_clk_read(&clk->base, nv_clk_src_dom6);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

206

return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

208

return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

210

return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

213

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

216

case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

223

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

224

case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

234

return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

235

return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

246

return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

249

return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

267

return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

268

return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

276

return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

282

return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

286

return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

288

return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

306

case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

308

case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

310

return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

406

out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

427

if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

430

if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

433

freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

56

u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

189

ref = nvkm_clk_read(clk, nv_clk_src_sppll0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

191

ref = nvkm_clk_read(clk, nv_clk_src_sppll1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

1122

nvkm_clk_read(clk, nv_clk_src_mem),

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c

187

clk_current = nvkm_clk_read(clk, nv_clk_src_mem);