nvif_rd32 - Linux

drivers/gpu/drm/nouveau/dispnv04/arb.c

202

uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);

drivers/gpu/drm/nouveau/dispnv04/arb.c

223

sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;

drivers/gpu/drm/nouveau/dispnv04/arb.c

224

sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;

drivers/gpu/drm/nouveau/dispnv04/dac.c

264

saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2);

drivers/gpu/drm/nouveau/dispnv04/dac.c

268

saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4);

drivers/gpu/drm/nouveau/dispnv04/dac.c

84

if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))

drivers/gpu/drm/nouveau/dispnv04/dac.c

90

if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))

drivers/gpu/drm/nouveau/dispnv04/dac.c

96

if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))

drivers/gpu/drm/nouveau/dispnv04/dfp.c

340

if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)

drivers/gpu/drm/nouveau/dispnv04/hw.c

178

pll1 = nvif_rd32(device, reg1);

drivers/gpu/drm/nouveau/dispnv04/hw.c

180

pll2 = nvif_rd32(device, reg1 + 4);

drivers/gpu/drm/nouveau/dispnv04/hw.c

184

pll2 = nvif_rd32(device, reg2);

drivers/gpu/drm/nouveau/dispnv04/hw.c

750

if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))

drivers/gpu/drm/nouveau/dispnv04/hw.c

754

if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))

drivers/gpu/drm/nouveau/dispnv04/hw.h

265

return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));

drivers/gpu/drm/nouveau/dispnv04/hw.h

66

val = nvif_rd32(device, reg);

drivers/gpu/drm/nouveau/dispnv04/hw.h

86

val = nvif_rd32(device, reg);

drivers/gpu/drm/nouveau/dispnv04/overlay.c

434

nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16));

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

140

return nvif_rd32(&device->object, reg);

drivers/gpu/drm/nouveau/dispnv50/disp.c

147

if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))

drivers/gpu/drm/nouveau/dispnv50/sorc37d.c

45

u32 tmp = nvif_rd32(&disp->caps, 0x000144 + (or * 8));

drivers/gpu/drm/nouveau/include/nvif/object.h

114

#define NVIF_RD32_(p,o,dr) nvif_rd32((p), (o) + (dr))

drivers/gpu/drm/nouveau/include/nvif/object.h

62

u32 _addr = (b), _data = nvif_rd32(__object, _addr); \

drivers/gpu/drm/nouveau/nouveau_backlight.c

104

if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))

drivers/gpu/drm/nouveau/nouveau_backlight.c

69

int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) &

drivers/gpu/drm/nouveau/nouveau_backlight.c

82

int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT);

drivers/gpu/drm/nouveau/nouveau_bios.c

1955

nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18);

drivers/gpu/drm/nouveau/nouveau_bios.c

240

sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;

drivers/gpu/drm/nouveau/nouveau_bios.c

336

return nvif_rd32(device, 0x001800) & 0x0000000f;

drivers/gpu/drm/nouveau/nouveau_bios.c

339

return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;

drivers/gpu/drm/nouveau/nouveau_bios.c

341

return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;

drivers/gpu/drm/nouveau/nouveau_bios.c

671

sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;

drivers/gpu/drm/nouveau/nouveau_debugfs.c

63

nvif_rd32(&drm->client.device.object, 0x101000));

drivers/gpu/drm/nouveau/nouveau_dma.c

45

val = nvif_rd32(chan->userd, chan->user_get);

drivers/gpu/drm/nouveau/nouveau_led.c

44

div = nvif_rd32(device, 0x61c880) & 0x00ffffff;

drivers/gpu/drm/nouveau/nouveau_led.c

45

duty = nvif_rd32(device, 0x61c884) & 0x00ffffff;

drivers/gpu/drm/nouveau/nouveau_svm.c

457

const u32 instlo = nvif_rd32(memory, offset + 0x00);

drivers/gpu/drm/nouveau/nouveau_svm.c

458

const u32 insthi = nvif_rd32(memory, offset + 0x04);

drivers/gpu/drm/nouveau/nouveau_svm.c

459

const u32 addrlo = nvif_rd32(memory, offset + 0x08);

drivers/gpu/drm/nouveau/nouveau_svm.c

460

const u32 addrhi = nvif_rd32(memory, offset + 0x0c);

drivers/gpu/drm/nouveau/nouveau_svm.c

461

const u32 timelo = nvif_rd32(memory, offset + 0x10);

drivers/gpu/drm/nouveau/nouveau_svm.c

462

const u32 timehi = nvif_rd32(memory, offset + 0x14);

drivers/gpu/drm/nouveau/nouveau_svm.c

463

const u32 engine = nvif_rd32(memory, offset + 0x18);

drivers/gpu/drm/nouveau/nouveau_svm.c

464

const u32 info = nvif_rd32(memory, offset + 0x1c);

drivers/gpu/drm/nouveau/nouveau_svm.c

734

buffer->put = nvif_rd32(device, buffer->putaddr);

drivers/gpu/drm/nouveau/nouveau_svm.c

735

buffer->get = nvif_rd32(device, buffer->getaddr);

drivers/gpu/drm/nouveau/nouveau_svm.c

956

buffer->get = nvif_rd32(device, buffer->getaddr);

drivers/gpu/drm/nouveau/nouveau_svm.c

957

buffer->put = nvif_rd32(device, buffer->putaddr);

drivers/gpu/drm/nouveau/nvif/chan506f.c

37

return nvif_rd32(&chan->userd, 0x88);

drivers/gpu/drm/nouveau/nvif/chan506f.c

43

u32 tlgetlo = nvif_rd32(&chan->userd, 0x58);

drivers/gpu/drm/nouveau/nvif/chan506f.c

44

u32 tlgethi = nvif_rd32(&chan->userd, 0x5c);

drivers/gpu/drm/nouveau/nvif/chan906f.c

56

return nvif_rd32(&chan->sema, 0) >> NVIF_CHAN906F_GPPTR_SHIFT;

drivers/gpu/drm/nouveau/nvif/chan906f.c

62

return nvif_rd32(&chan->sema, 0) & NVIF_CHAN906F_PBPTR_MASK;

drivers/gpu/drm/nouveau/nvif/chanc36f.c

19

nvif_rd32(&chan->userd, 0); /* ensure BAR1 writes are flushed to vidmem */

drivers/gpu/drm/nouveau/nvif/userc361.c

30

hi = nvif_rd32(&user->object, 0x084);

drivers/gpu/drm/nouveau/nvif/userc361.c

31

lo = nvif_rd32(&user->object, 0x080);

drivers/gpu/drm/nouveau/nvif/userc361.c

32

} while (hi != nvif_rd32(&user->object, 0x084));