drivers/gpu/drm/nouveau/include/nvkm/core/layout.h

46

NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 8)

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

1907

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

1975

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2010

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2045

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2103

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2136

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2170

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2204

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2238

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2272

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2332

.nvdec = { 0x00000001, gm107_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2367

.nvdec = { 0x00000001, tu102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2402

.nvdec = { 0x00000003, tu102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2437

.nvdec = { 0x00000007, tu102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2472

.nvdec = { 0x00000001, tu102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2507

.nvdec = { 0x00000001, tu102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2561

.nvdec = { 0x00000003, ga102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2591

.nvdec = { 0x00000003, ga102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2621

.nvdec = { 0x00000003, ga102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2651

.nvdec = { 0x00000003, ga102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

2681

.nvdec = { 0x00000003, ga102_nvdec_new },

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

28

struct nvkm_nvdec *nvdec = nvkm_nvdec(engine);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

29

nvkm_falcon_dtor(&nvdec->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

30

return nvdec;

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

43

struct nvkm_nvdec *nvdec;

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

46

if (!(nvdec = *pnvdec = kzalloc_obj(*nvdec)))

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

50

&nvdec->engine);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

54

fwif = nvkm_firmware_load(&nvdec->engine.subdev, fwif, "Nvdec", nvdec);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

58

nvdec->func = fwif->func;

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

60

return nvkm_falcon_ctor(nvdec->func->flcn, &nvdec->engine.subdev,

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

61

nvdec->engine.subdev.name, addr, &nvdec->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.c

44

ga102_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver, const struct nvkm_nvdec_fwif *fwif)

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c

41

gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c

40

0, &subdev->device->nvdec[0]->falcon, &fb->vpr_scrubber);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c

63

0, &subdev->device->nvdec[0]->falcon, &fb->vpr_scrubber);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c

36

.nvdec.class = NVC9B0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c

165

if (WARN_ON(inst >= ARRAY_SIZE(device->nvdec)))

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c

59

ret = rm->api->nvdec->alloc(chan, handle, class, inst, &obj->rm);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga100.c

27

.nvdec.class = NVC6B0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c

36

.nvdec.class = NVC7B0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb10x.c

27

.nvdec.class = NVCDB0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb20x.c

40

.nvdec.class = NVCFB0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gh100.c

27

.nvdec.class = NVB8B0_VIDEO_DECODER,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h

48

} nvdec;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

17

struct nvkm_nvdec *nvdec;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

20

nvdec = kzalloc_obj(*nvdec);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

21

if (!nvdec)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

25

&rm->gpu->nvdec.class, 1, &nvdec->engine);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

27

kfree(nvdec);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c

31

rm->device->nvdec[inst] = nvdec;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvdec.c

28

struct nvkm_gsp_object *nvdec)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvdec.c

32

args = nvkm_gsp_rm_alloc_get(chan, handle, class, sizeof(*args), nvdec);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvdec.c

39

return nvkm_gsp_rm_alloc_wr(nvdec, args);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rm.c

36

.nvdec = &r535_nvdec,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/rm.c

65

.nvdec = &r535_nvdec,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h

124

} *ce, *nvdec, *nvenc, *nvjpg, *ofa;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c

36

.nvdec.class = NVC4B0_VIDEO_DECODER,

drivers/gpu/drm/tegra/nvdec.c

101

dev_err(nvdec->dev, "failed to boot %s, debuginfo=0x%x\n", phase, val);

drivers/gpu/drm/tegra/nvdec.c

108

static int nvdec_boot_riscv(struct nvdec *nvdec)

drivers/gpu/drm/tegra/nvdec.c

112

err = reset_control_acquire(nvdec->reset);

drivers/gpu/drm/tegra/nvdec.c

116

nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);

drivers/gpu/drm/tegra/nvdec.c

118

err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,

drivers/gpu/drm/tegra/nvdec.c

119

&nvdec->riscv.bl_desc);

drivers/gpu/drm/tegra/nvdec.c

121

dev_err(nvdec->dev, "failed to execute bootloader\n");

drivers/gpu/drm/tegra/nvdec.c

125

err = nvdec_wait_debuginfo(nvdec, "bootloader");

drivers/gpu/drm/tegra/nvdec.c

129

err = reset_control_reset(nvdec->reset);

drivers/gpu/drm/tegra/nvdec.c

133

nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);

drivers/gpu/drm/tegra/nvdec.c

135

err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,

drivers/gpu/drm/tegra/nvdec.c

136

&nvdec->riscv.os_desc);

drivers/gpu/drm/tegra/nvdec.c

138

dev_err(nvdec->dev, "failed to execute firmware\n");

drivers/gpu/drm/tegra/nvdec.c

142

err = nvdec_wait_debuginfo(nvdec, "firmware");

drivers/gpu/drm/tegra/nvdec.c

147

reset_control_release(nvdec->reset);

drivers/gpu/drm/tegra/nvdec.c

157

struct nvdec *nvdec = to_nvdec(drm);

drivers/gpu/drm/tegra/nvdec.c

162

dev_err(nvdec->dev, "failed to attach to domain: %d\n", err);

drivers/gpu/drm/tegra/nvdec.c

166

nvdec->channel = host1x_channel_request(client);

drivers/gpu/drm/tegra/nvdec.c

167

if (!nvdec->channel) {

drivers/gpu/drm/tegra/nvdec.c

193

host1x_channel_put(nvdec->channel);

drivers/gpu/drm/tegra/nvdec.c

205

struct nvdec *nvdec = to_nvdec(drm);

drivers/gpu/drm/tegra/nvdec.c

219

host1x_channel_put(nvdec->channel);

drivers/gpu/drm/tegra/nvdec.c

222

nvdec->channel = NULL;

drivers/gpu/drm/tegra/nvdec.c

225

dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys,

drivers/gpu/drm/tegra/nvdec.c

226

nvdec->falcon.firmware.size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/nvdec.c

227

tegra_drm_free(tegra, nvdec->falcon.firmware.size,

drivers/gpu/drm/tegra/nvdec.c

228

nvdec->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvdec.c

229

nvdec->falcon.firmware.iova);

drivers/gpu/drm/tegra/nvdec.c

231

dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size,

drivers/gpu/drm/tegra/nvdec.c

232

nvdec->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvdec.c

233

nvdec->falcon.firmware.iova);

drivers/gpu/drm/tegra/nvdec.c

244

static int nvdec_load_falcon_firmware(struct nvdec *nvdec)

drivers/gpu/drm/tegra/nvdec.c

246

struct host1x_client *client = &nvdec->client.base;

drivers/gpu/drm/tegra/nvdec.c

247

struct tegra_drm *tegra = nvdec->client.drm;

drivers/gpu/drm/tegra/nvdec.c

253

if (nvdec->falcon.firmware.virt)

drivers/gpu/drm/tegra/nvdec.c

256

err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);

drivers/gpu/drm/tegra/nvdec.c

260

size = nvdec->falcon.firmware.size;

drivers/gpu/drm/tegra/nvdec.c

263

virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL);

drivers/gpu/drm/tegra/nvdec.c

272

nvdec->falcon.firmware.virt = virt;

drivers/gpu/drm/tegra/nvdec.c

273

nvdec->falcon.firmware.iova = iova;

drivers/gpu/drm/tegra/nvdec.c

275

err = falcon_load_firmware(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

287

phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/nvdec.c

289

err = dma_mapping_error(nvdec->dev, phys);

drivers/gpu/drm/tegra/nvdec.c

293

nvdec->falcon.firmware.phys = phys;

drivers/gpu/drm/tegra/nvdec.c

300

dma_free_coherent(nvdec->dev, size, virt, iova);

drivers/gpu/drm/tegra/nvdec.c

309

struct nvdec *nvdec = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/nvdec.c

312

err = clk_bulk_prepare_enable(nvdec->num_clks, nvdec->clks);

drivers/gpu/drm/tegra/nvdec.c

318

if (nvdec->config->has_riscv) {

drivers/gpu/drm/tegra/nvdec.c

319

err = nvdec_boot_riscv(nvdec);

drivers/gpu/drm/tegra/nvdec.c

323

err = nvdec_load_falcon_firmware(nvdec);

drivers/gpu/drm/tegra/nvdec.c

327

err = nvdec_boot_falcon(nvdec);

drivers/gpu/drm/tegra/nvdec.c

335

clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);

drivers/gpu/drm/tegra/nvdec.c

341

struct nvdec *nvdec = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/nvdec.c

343

host1x_channel_stop(nvdec->channel);

drivers/gpu/drm/tegra/nvdec.c

345

clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);

drivers/gpu/drm/tegra/nvdec.c

353

struct nvdec *nvdec = to_nvdec(client);

drivers/gpu/drm/tegra/nvdec.c

355

context->channel = host1x_channel_get(nvdec->channel);

drivers/gpu/drm/tegra/nvdec.c

426

struct nvdec *nvdec;

drivers/gpu/drm/tegra/nvdec.c

437

nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL);

drivers/gpu/drm/tegra/nvdec.c

438

if (!nvdec)

drivers/gpu/drm/tegra/nvdec.c

441

nvdec->config = of_device_get_match_data(dev);

drivers/gpu/drm/tegra/nvdec.c

447

nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);

drivers/gpu/drm/tegra/nvdec.c

448

if (IS_ERR(nvdec->regs))

drivers/gpu/drm/tegra/nvdec.c

449

return PTR_ERR(nvdec->regs);

drivers/gpu/drm/tegra/nvdec.c

451

nvdec->clks[0].id = "nvdec";

drivers/gpu/drm/tegra/nvdec.c

452

nvdec->num_clks = 1;

drivers/gpu/drm/tegra/nvdec.c

454

if (nvdec->config->has_extra_clocks) {

drivers/gpu/drm/tegra/nvdec.c

455

nvdec->num_clks = 3;

drivers/gpu/drm/tegra/nvdec.c

456

nvdec->clks[1].id = "fuse";

drivers/gpu/drm/tegra/nvdec.c

457

nvdec->clks[2].id = "tsec_pka";

drivers/gpu/drm/tegra/nvdec.c

460

err = devm_clk_bulk_get(dev, nvdec->num_clks, nvdec->clks);

drivers/gpu/drm/tegra/nvdec.c

466

err = clk_set_rate(nvdec->clks[0].clk, ULONG_MAX);

drivers/gpu/drm/tegra/nvdec.c

476

if (nvdec->config->has_riscv) {

drivers/gpu/drm/tegra/nvdec.c

486

err = tegra_mc_get_carveout_info(mc, 1, &nvdec->carveout_base, NULL);

drivers/gpu/drm/tegra/nvdec.c

492

nvdec->reset = devm_reset_control_get_exclusive_released(dev, "nvdec");

drivers/gpu/drm/tegra/nvdec.c

493

if (IS_ERR(nvdec->reset)) {

drivers/gpu/drm/tegra/nvdec.c

494

dev_err_probe(dev, PTR_ERR(nvdec->reset), "failed to get reset\n");

drivers/gpu/drm/tegra/nvdec.c

495

return PTR_ERR(nvdec->reset);

drivers/gpu/drm/tegra/nvdec.c

498

nvdec->riscv.dev = dev;

drivers/gpu/drm/tegra/nvdec.c

499

nvdec->riscv.regs = nvdec->regs;

drivers/gpu/drm/tegra/nvdec.c

501

err = tegra_drm_riscv_read_descriptors(&nvdec->riscv);

drivers/gpu/drm/tegra/nvdec.c

505

nvdec->falcon.dev = dev;

drivers/gpu/drm/tegra/nvdec.c

506

nvdec->falcon.regs = nvdec->regs;

drivers/gpu/drm/tegra/nvdec.c

508

err = falcon_init(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

513

platform_set_drvdata(pdev, nvdec);

drivers/gpu/drm/tegra/nvdec.c

515

INIT_LIST_HEAD(&nvdec->client.base.list);

drivers/gpu/drm/tegra/nvdec.c

516

nvdec->client.base.ops = &nvdec_client_ops;

drivers/gpu/drm/tegra/nvdec.c

517

nvdec->client.base.dev = dev;

drivers/gpu/drm/tegra/nvdec.c

518

nvdec->client.base.class = host_class;

drivers/gpu/drm/tegra/nvdec.c

519

nvdec->client.base.syncpts = syncpts;

drivers/gpu/drm/tegra/nvdec.c

520

nvdec->client.base.num_syncpts = 1;

drivers/gpu/drm/tegra/nvdec.c

521

nvdec->dev = dev;

drivers/gpu/drm/tegra/nvdec.c

523

INIT_LIST_HEAD(&nvdec->client.list);

drivers/gpu/drm/tegra/nvdec.c

524

nvdec->client.version = nvdec->config->version;

drivers/gpu/drm/tegra/nvdec.c

525

nvdec->client.ops = &nvdec_ops;

drivers/gpu/drm/tegra/nvdec.c

527

err = host1x_client_register(&nvdec->client.base);

drivers/gpu/drm/tegra/nvdec.c

540

falcon_exit(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

547

struct nvdec *nvdec = platform_get_drvdata(pdev);

drivers/gpu/drm/tegra/nvdec.c

55

static inline struct nvdec *to_nvdec(struct tegra_drm_client *client)

drivers/gpu/drm/tegra/nvdec.c

550

host1x_client_unregister(&nvdec->client.base);

drivers/gpu/drm/tegra/nvdec.c

551

falcon_exit(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

57

return container_of(client, struct nvdec, client);

drivers/gpu/drm/tegra/nvdec.c

60

static inline void nvdec_writel(struct nvdec *nvdec, u32 value,

drivers/gpu/drm/tegra/nvdec.c

63

writel(value, nvdec->regs + offset);

drivers/gpu/drm/tegra/nvdec.c

66

static int nvdec_boot_falcon(struct nvdec *nvdec)

drivers/gpu/drm/tegra/nvdec.c

71

if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) {

drivers/gpu/drm/tegra/nvdec.c

75

nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);

drivers/gpu/drm/tegra/nvdec.c

77

nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID0);

drivers/gpu/drm/tegra/nvdec.c

78

nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID1);

drivers/gpu/drm/tegra/nvdec.c

81

err = falcon_boot(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

85

err = falcon_wait_idle(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

87

dev_err(nvdec->dev, "falcon boot timed out\n");

drivers/gpu/drm/tegra/nvdec.c

94

static int nvdec_wait_debuginfo(struct nvdec *nvdec, const char *phase)

drivers/gpu/drm/tegra/nvdec.c

99

err = readl_poll_timeout(nvdec->regs + NVDEC_FALCON_DEBUGINFO, val, val == 0x0, 10, 100000);