nv_clk_src_gpc
case nv_clk_src_gpc:
if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
{ nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_VPSTATE, "core", 2000 },
case nv_clk_src_gpc:
if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE | NVKM_CLK_DOM_FLAG_VPSTATE, "core", 2000 },
.domain[nv_clk_src_gpc] = 72000,
.domain[nv_clk_src_gpc] = 108000,
.domain[nv_clk_src_gpc] = 180000,
.domain[nv_clk_src_gpc] = 252000,
.domain[nv_clk_src_gpc] = 324000,
.domain[nv_clk_src_gpc] = 396000,
.domain[nv_clk_src_gpc] = 468000,
.domain[nv_clk_src_gpc] = 540000,
.domain[nv_clk_src_gpc] = 612000,
.domain[nv_clk_src_gpc] = 648000,
.domain[nv_clk_src_gpc] = 684000,
.domain[nv_clk_src_gpc] = 708000,
.domain[nv_clk_src_gpc] = 756000,
.domain[nv_clk_src_gpc] = 804000,
.domain[nv_clk_src_gpc] = 852000,
case nv_clk_src_gpc:
return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
if (pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV >= *freq)
*freq = pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV;
*freq = nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;
pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV, 0);
nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;
pstates[i].base.domain[nv_clk_src_gpc]);
ret = gk20a_pllg_calc_mnp(&clk->base, cstate->domain[nv_clk_src_gpc] *
cur_freq = nvkm_clk_read(&clk->base.base, nv_clk_src_gpc);
.domain[nv_clk_src_gpc] = 76800,
.domain[nv_clk_src_gpc] = 153600,
.domain[nv_clk_src_gpc] = 230400,
.domain[nv_clk_src_gpc] = 307200,
.domain[nv_clk_src_gpc] = 384000,
.domain[nv_clk_src_gpc] = 460800,
.domain[nv_clk_src_gpc] = 537600,
.domain[nv_clk_src_gpc] = 614400,
.domain[nv_clk_src_gpc] = 691200,
.domain[nv_clk_src_gpc] = 768000,
.domain[nv_clk_src_gpc] = 844800,
.domain[nv_clk_src_gpc] = 921600,
.domain[nv_clk_src_gpc] = 998400,
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
.domain[nv_clk_src_gpc] = 624750,
.domain[nv_clk_src_gpc] = 726750,
.domain[nv_clk_src_gpc] = 828750,
.domain[nv_clk_src_gpc] = 930750,
.domain[nv_clk_src_gpc] = 1032750,
.domain[nv_clk_src_gpc] = 1134750,
.domain[nv_clk_src_gpc] = 1236750,
.domain[nv_clk_src_gpc] = 1300500,
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
case nv_clk_src_gpc:
u32 target_rate = cstate->domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV;
.domain[nv_clk_src_gpc] = 114750,
.domain[nv_clk_src_gpc] = 216750,
.domain[nv_clk_src_gpc] = 318750,
.domain[nv_clk_src_gpc] = 420750,
.domain[nv_clk_src_gpc] = 522750,