drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

125

read_pll_ref(struct nv50_clk *clk, u32 base)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

158

read_pll(struct nv50_clk *clk, u32 base)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

194

struct nv50_clk *clk = nv50_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

32

read_div(struct nv50_clk *clk)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

326

calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

371

struct nv50_clk *clk = nv50_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

498

struct nv50_clk *clk = nv50_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

505

struct nv50_clk *clk = nv50_clk(base);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

513

struct nv50_clk *clk;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

52

read_pll_src(struct nv50_clk *clk, u32 base)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

543

nv50_clk = {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

562

return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h

4

#define nv50_clk(p) container_of((p), struct nv50_clk, base)