drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1005

struct nv10_gr *gr = nv10_gr(base);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1051

struct nv10_gr *gr = nv10_gr(base);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1083

struct nv10_gr *gr = nv10_gr(base);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1138

struct nv10_gr *gr = nv10_gr(base);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1178

struct nv10_gr *gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1189

nv10_gr = {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

1220

return nv10_gr_new_(&nv10_gr, device, type, inst, pgr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

389

#define nv10_gr(p) container_of((p), struct nv10_gr, base)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

401

struct nv10_gr *gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

547

nv10_gr_channel(struct nv10_gr *gr)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

562

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

581

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

632

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

786

nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

799

nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

814

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

885

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

912

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

932

nv10_gr_context_switch(struct nv10_gr *gr)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

957

struct nv10_gr *gr = chan->gr;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

974

struct nv10_gr *gr = chan->gr;