drivers/perf/marvell_cn10k_ddr_pmu.c

205

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

206

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

207

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

208

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW),

drivers/perf/marvell_cn10k_ddr_pmu.c

209

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

210

CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS),

drivers/perf/marvell_cn10k_ddr_pmu.c

211

CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS),

drivers/perf/marvell_cn10k_ddr_pmu.c

212

CN10K_DDR_PMU_EVENT_ATTR(ddr_dif_wr_data_access, EVENT_DFI_WR_DATA_CYCLES),

drivers/perf/marvell_cn10k_ddr_pmu.c

213

CN10K_DDR_PMU_EVENT_ATTR(ddr_dif_rd_data_access, EVENT_DFI_RD_DATA_CYCLES),

drivers/perf/marvell_cn10k_ddr_pmu.c

214

CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

216

CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

218

CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

220

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE),

drivers/perf/marvell_cn10k_ddr_pmu.c

221

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access, EVENT_OP_IS_RD_OR_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

222

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access, EVENT_OP_IS_RD_ACTIVATE),

drivers/perf/marvell_cn10k_ddr_pmu.c

223

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

224

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

225

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR),

drivers/perf/marvell_cn10k_ddr_pmu.c

226

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE),

drivers/perf/marvell_cn10k_ddr_pmu.c

227

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr, EVENT_PRECHARGE_FOR_RDWR),

drivers/perf/marvell_cn10k_ddr_pmu.c

228

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other,

drivers/perf/marvell_cn10k_ddr_pmu.c

230

CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS),

drivers/perf/marvell_cn10k_ddr_pmu.c

231

CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE),

drivers/perf/marvell_cn10k_ddr_pmu.c

232

CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

233

CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

234

CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

235

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF),

drivers/perf/marvell_cn10k_ddr_pmu.c

236

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown, EVENT_OP_IS_ENTER_POWERDOWN),

drivers/perf/marvell_cn10k_ddr_pmu.c

237

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_mpsm, EVENT_OP_IS_ENTER_MPSM),

drivers/perf/marvell_cn10k_ddr_pmu.c

238

CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH),

drivers/perf/marvell_cn10k_ddr_pmu.c

239

CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF),

drivers/perf/marvell_cn10k_ddr_pmu.c

240

CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF),

drivers/perf/marvell_cn10k_ddr_pmu.c

241

CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE),

drivers/perf/marvell_cn10k_ddr_pmu.c

242

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL),

drivers/perf/marvell_cn10k_ddr_pmu.c

243

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS),

drivers/perf/marvell_cn10k_ddr_pmu.c

244

CN10K_DDR_PMU_EVENT_ATTR(ddr_hpr_req_with_nocredit,

drivers/perf/marvell_cn10k_ddr_pmu.c

246

CN10K_DDR_PMU_EVENT_ATTR(ddr_lpr_req_with_nocredit,

drivers/perf/marvell_cn10k_ddr_pmu.c

248

CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC),

drivers/perf/marvell_cn10k_ddr_pmu.c

249

CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION),

drivers/perf/marvell_cn10k_ddr_pmu.c

250

CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,

drivers/perf/marvell_cn10k_ddr_pmu.c

252

CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr,

drivers/perf/marvell_cn10k_ddr_pmu.c

254

CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_OP_IS_DQSOSC_MPC),

drivers/perf/marvell_cn10k_ddr_pmu.c

255

CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_OP_IS_DQSOSC_MRR),

drivers/perf/marvell_cn10k_ddr_pmu.c

256

CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_OP_IS_TCR_MRR),

drivers/perf/marvell_cn10k_ddr_pmu.c

257

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_OP_IS_ZQSTART),

drivers/perf/marvell_cn10k_ddr_pmu.c

258

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_OP_IS_ZQLATCH),

drivers/perf/marvell_cn10k_ddr_pmu.c

260

CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS),

drivers/perf/marvell_cn10k_ddr_pmu.c

261

CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES),

drivers/perf/marvell_cn10k_ddr_pmu.c

267

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

268

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

269

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

270

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW),

drivers/perf/marvell_cn10k_ddr_pmu.c

271

CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

272

CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS),

drivers/perf/marvell_cn10k_ddr_pmu.c

273

CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS),

drivers/perf/marvell_cn10k_ddr_pmu.c

274

CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_wr_data_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

276

CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_rd_data_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

278

CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

280

CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

282

CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

284

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE),

drivers/perf/marvell_cn10k_ddr_pmu.c

285

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

287

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access,

drivers/perf/marvell_cn10k_ddr_pmu.c

289

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD),

drivers/perf/marvell_cn10k_ddr_pmu.c

290

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR),

drivers/perf/marvell_cn10k_ddr_pmu.c

291

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR),

drivers/perf/marvell_cn10k_ddr_pmu.c

292

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE),

drivers/perf/marvell_cn10k_ddr_pmu.c

293

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr,

drivers/perf/marvell_cn10k_ddr_pmu.c

295

CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other,

drivers/perf/marvell_cn10k_ddr_pmu.c

297

CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS),

drivers/perf/marvell_cn10k_ddr_pmu.c

298

CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE),

drivers/perf/marvell_cn10k_ddr_pmu.c

299

CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

300

CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

301

CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD),

drivers/perf/marvell_cn10k_ddr_pmu.c

302

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF),

drivers/perf/marvell_cn10k_ddr_pmu.c

303

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown,

drivers/perf/marvell_cn10k_ddr_pmu.c

305

CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_mpsm, EVENT_OP_IS_ENTER_MPSM),

drivers/perf/marvell_cn10k_ddr_pmu.c

306

CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH),

drivers/perf/marvell_cn10k_ddr_pmu.c

307

CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF),

drivers/perf/marvell_cn10k_ddr_pmu.c

308

CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF),

drivers/perf/marvell_cn10k_ddr_pmu.c

309

CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE),

drivers/perf/marvell_cn10k_ddr_pmu.c

310

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL),

drivers/perf/marvell_cn10k_ddr_pmu.c

311

CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS),

drivers/perf/marvell_cn10k_ddr_pmu.c

312

CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cycles, EVENT_DFI_CYCLES),

drivers/perf/marvell_cn10k_ddr_pmu.c

313

CN10K_DDR_PMU_EVENT_ATTR(ddr_retry_fifo_full,

drivers/perf/marvell_cn10k_ddr_pmu.c

315

CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC),

drivers/perf/marvell_cn10k_ddr_pmu.c

316

CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION),

drivers/perf/marvell_cn10k_ddr_pmu.c

317

CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,

drivers/perf/marvell_cn10k_ddr_pmu.c

319

CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr,

drivers/perf/marvell_cn10k_ddr_pmu.c

321

CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_OP_IS_DQSOSC_MPC),

drivers/perf/marvell_cn10k_ddr_pmu.c

322

CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_OP_IS_DQSOSC_MRR),

drivers/perf/marvell_cn10k_ddr_pmu.c

323

CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_OP_IS_TCR_MRR),

drivers/perf/marvell_cn10k_ddr_pmu.c

324

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_OP_IS_ZQSTART),

drivers/perf/marvell_cn10k_ddr_pmu.c

325

CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_OP_IS_ZQLATCH),

drivers/perf/marvell_cn10k_ddr_pmu.c

326

CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_parity_poison,

drivers/perf/marvell_cn10k_ddr_pmu.c

328

CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_crc_error, EVENT_WR_CRC_ERROR),

drivers/perf/marvell_cn10k_ddr_pmu.c

329

CN10K_DDR_PMU_EVENT_ATTR(ddr_capar_error, EVENT_CAPAR_ERROR),

drivers/perf/marvell_cn10k_ddr_pmu.c

330

CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_crc_error, EVENT_RD_CRC_ERROR),

drivers/perf/marvell_cn10k_ddr_pmu.c

331

CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_uc_ecc_error, EVENT_RD_UC_ECC_ERROR),

drivers/perf/marvell_cn10k_ddr_pmu.c

332

CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cmd_is_retry, EVENT_DFI_CMD_IS_RETRY),

drivers/perf/marvell_cn10k_ddr_pmu.c

334

CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS),

drivers/perf/marvell_cn10k_ddr_pmu.c

335

CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES),