nr64
sig = nr64(ESR_INT_SIGNALS);
val = nr64(MIF_CONFIG);
val = nr64(MIF_CONFIG);
val = nr64(MIF_CONFIG);
val = nr64(MIF_CONFIG);
u64 val = nr64(reg);
sig = nr64(ESR_INT_SIGNALS);
(unsigned long long)nr64(reg));
sig = nr64(ESR_INT_SIGNALS);
val = nr64(mask_reg);
u64 reg_val = nr64(ENET_VLAN_TBL(index));
if (nr64(TCAM_CTL) & bit)
key[0] = nr64(TCAM_KEY_0);
key[1] = nr64(TCAM_KEY_1);
key[2] = nr64(TCAM_KEY_2);
key[3] = nr64(TCAM_KEY_3);
mask[0] = nr64(TCAM_KEY_MASK_0);
mask[1] = nr64(TCAM_KEY_MASK_1);
mask[2] = nr64(TCAM_KEY_MASK_2);
mask[3] = nr64(TCAM_KEY_MASK_3);
*data = nr64(TCAM_KEY_1);
u64 val = nr64(FFLP_CFG_1);
u64 val = nr64(FFLP_CFG_1);
val = nr64(FFLP_CFG_1);
val = nr64(reg);
val = nr64(reg);
val = nr64(reg);
val = nr64(reg);
data[i] = nr64(HASH_TBL_DATA(partition));
u64 val = nr64(FFLP_CFG_1);
val = nr64(FFLP_CFG_1);
val = nr64(FCRAM_REF_TMR);
val = nr64(reg);
u64 val = nr64(FFLP_CFG_1);
u64 val = nr64(FFLP_CFG_1);
val = nr64(MIF_FRAME_OUTPUT);
misc = nr64(RXMISC(rx_channel));
wred = nr64(RED_DIS_CNT(rx_channel));
stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
cs = nr64(TX_CS(rp->tx_channel));
logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
u64 mif_status = nr64(MIF_STATUS);
u64 stat = nr64(SYS_ERR_STAT);
rp->tx_cs = nr64(TX_CS(rp->tx_channel));
v0 = nr64(LDSV0(ldg));
v1 = nr64(LDSV1(ldg));
v2 = nr64(LDSV2(ldg));
u64 val = nr64(TX_CS(channel));
u64 val = nr64(TX_CS(channel));
u64 val = nr64(TX_CS(channel));
u64 val = nr64(TX_CS(channel));
val = nr64(TXC_CONTROL);
val = nr64(TXC_INT_MASK);
u64 val = nr64(RXDMA_CFIG1(channel));
if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
val = nr64(RX_DMA_CTL_STAT(channel));
(unsigned long long)nr64(ZCP_RAM_ACC));
(unsigned long long)nr64(ZCP_RAM_ACC));
data[0] = nr64(ZCP_RAM_DATA0);
data[1] = nr64(ZCP_RAM_DATA1);
data[2] = nr64(ZCP_RAM_DATA2);
data[3] = nr64(ZCP_RAM_DATA3);
data[4] = nr64(ZCP_RAM_DATA4);
u64 val = nr64(RESET_CFIFO);
(void) nr64(ZCP_INT_STAT);
sig = nr64(ESR_INT_SIGNALS);
val = nr64(MIF_CONFIG);
sig = nr64(ESR_INT_SIGNALS);
val = nr64(ESPC_NCR((offset - b_offset) / 4));
val = nr64(ESPC_NCR(offset / 4));
val = nr64(ESPC_NCR(offset / 4));
if (nr64(LDG_NUM(ldn)) != ldg) {
(unsigned long long) nr64(LDG_NUM(ldn)));
frame = nr64(ESPC_PIO_STAT);
frame = nr64(ESPC_PIO_STAT);
frame = nr64(ESPC_PIO_STAT);
val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
val = nr64(ESPC_NCR(i));
val = nr64(ESPC_PHY_TYPE);
val = nr64(ESPC_MAC_ADDR0);
val = nr64(ESPC_MAC_ADDR1);
val = nr64(ESPC_MOD_STR_LEN);
u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
val = nr64(ESPC_BD_MOD_STR_LEN);
u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
sig = nr64(ESR_INT_SIGNALS);
parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
val = nr64(ENET_SERDES_1_PLL_CFG);
val_rd = nr64(ENET_SERDES_RESET);