Symbol: CM_GCR_Cx_RESET64_BASE_BEVEXCBASE
arch/mips/kernel/smp-cps.c
146
write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE);
arch/mips/kernel/smp-cps.c
147
if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) ==
arch/mips/kernel/smp-cps.c
148
CM_GCR_Cx_RESET64_BASE_BEVEXCBASE)
arch/mips/kernel/smp-cps.c
177
core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) |