nixge_ctrl_write_reg
nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,