nixge_dma_write_reg
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);
nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);
nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,