CMR
ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
regs + ATMEL_TC_REG(2, CMR));
tcaddr + ATMEL_TC_REG(0, CMR));
tcaddr + ATMEL_TC_REG(1, CMR));
tcaddr + ATMEL_TC_REG(0, CMR));
tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
ATMEL_TC_REG(priv->channel[1], CMR), cmr);
regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
ATMEL_TC_REG(priv->channel[0], CMR),
ret = regmap_update_bits(regmap, ATMEL_TC_REG(priv->channel[0], CMR),
regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
write_reg_le32(par->dc_regs, CMR, 0x00ff);
write_reg_le32(par->dc_regs, CMR, 0x01ff);
ssc_writel(ssc_p->ssc->regs, CMR, cmr_div);
ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
ssc_writel(chip->ssc->regs, CMR, ssc_div/2);