nau8540
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
nau8540_get_osr(struct nau8540 *nau8540)
regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
osr = nau8540_get_osr(nau8540);
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
osr = nau8540_get_osr(nau8540);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8540->regmap;
dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val);
dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val);
dev_err(nau8540->dev, "Channel recovery failed!!");
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
nau8540_fll_apply(nau8540->regmap, &fll_param);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
static void nau8540_init_regs(struct nau8540 *nau8540)
struct regmap *regmap = nau8540->regmap;
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regcache_cache_only(nau8540->regmap, true);
regcache_mark_dirty(nau8540->regmap);
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regcache_cache_only(nau8540->regmap, false);
regcache_sync(nau8540->regmap);
struct nau8540 *nau8540 = dev_get_platdata(dev);
if (!nau8540) {
nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
if (!nau8540)
i2c_set_clientdata(i2c, nau8540);
nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
if (IS_ERR(nau8540->regmap))
return PTR_ERR(nau8540->regmap);
ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
nau8540->dev = dev;
nau8540_reset_chip(nau8540->regmap);
nau8540_init_regs(nau8540);