arch/riscv/include/asm/kvm_nacl.h

226

nacl_csr_write(nacl_shmem(), __csr, __val); \

arch/riscv/kvm/aia.c

137

nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect);

arch/riscv/kvm/aia.c

138

nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1);

arch/riscv/kvm/aia.c

139

nacl_csr_write(nsh, CSR_HVIPRIO2, csr->hviprio2);

arch/riscv/kvm/aia.c

141

nacl_csr_write(nsh, CSR_VSIEH, csr->vsieh);

arch/riscv/kvm/aia.c

142

nacl_csr_write(nsh, CSR_HVIPH, csr->hviph);

arch/riscv/kvm/aia.c

143

nacl_csr_write(nsh, CSR_HVIPRIO1H, csr->hviprio1h);

arch/riscv/kvm/aia.c

144

nacl_csr_write(nsh, CSR_HVIPRIO2H, csr->hviprio2h);

arch/riscv/kvm/vcpu.c

603

nacl_csr_write(nsh, CSR_VSSTATUS, csr->vsstatus);

arch/riscv/kvm/vcpu.c

604

nacl_csr_write(nsh, CSR_VSIE, csr->vsie);

arch/riscv/kvm/vcpu.c

605

nacl_csr_write(nsh, CSR_VSTVEC, csr->vstvec);

arch/riscv/kvm/vcpu.c

606

nacl_csr_write(nsh, CSR_VSSCRATCH, csr->vsscratch);

arch/riscv/kvm/vcpu.c

607

nacl_csr_write(nsh, CSR_VSEPC, csr->vsepc);

arch/riscv/kvm/vcpu.c

608

nacl_csr_write(nsh, CSR_VSCAUSE, csr->vscause);

arch/riscv/kvm/vcpu.c

609

nacl_csr_write(nsh, CSR_VSTVAL, csr->vstval);

arch/riscv/kvm/vcpu.c

610

nacl_csr_write(nsh, CSR_HVIP, csr->hvip);

arch/riscv/kvm/vcpu.c

611

nacl_csr_write(nsh, CSR_VSATP, csr->vsatp);

arch/riscv/kvm/vcpu_config.c

81

nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);

arch/riscv/kvm/vcpu_config.c

82

nacl_csr_write(nsh, CSR_HIDELEG, cfg->hideleg);

arch/riscv/kvm/vcpu_config.c

83

nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);

arch/riscv/kvm/vcpu_config.c

85

nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);

arch/riscv/kvm/vcpu_config.c

87

nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0);

arch/riscv/kvm/vcpu_config.c

89

nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32);