CMN_REFCLK1_DIG_DIV
sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);