mvpp2_read
u32 mvpp2_read(struct mvpp2 *priv, u32 offset);
val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
return mvpp2_read(priv, MVPP2_CLS_FLOW_TBL_HIT_CTR);
fe->data[0] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL0_REG);
fe->data[1] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL1_REG);
fe->data[2] = mvpp2_read(priv, MVPP2_CLS_FLOW_TBL2_REG);
return mvpp2_read(priv, MVPP2_CLS_DEC_TBL_HIT_CTR);
le->data = mvpp2_read(priv, MVPP2_CLS_LKP_TBL_REG);
val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV);
c2->tcam[0] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA0);
c2->tcam[1] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA1);
c2->tcam[2] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA2);
c2->tcam[3] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA3);
c2->tcam[4] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA4);
c2->act = mvpp2_read(priv, MVPP22_CLS_C2_ACT);
c2->attr[0] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR0);
c2->attr[1] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR1);
c2->attr[2] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR2);
c2->attr[3] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR3);
val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV);
val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
return mvpp2_read(priv, MVPP22_CLS_C2_HIT_CTR);
return mvpp2_read(priv, reg);
*pstats++ += mvpp2_read(port->priv,
val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
val = mvpp2_read(port->priv,
val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
aggr_txq->next_desc_to_proc = mvpp2_read(priv,
val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id));
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id));
reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id));
val = mvpp2_read(priv, MVPP2_PRS_TCAM_HIT_CNT_REG);
pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));