mv88e6xxx_port_write
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_LED_CONTROL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_LED_CONTROL, ptr);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE,
err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
err = mv88e6xxx_port_write(chip, port,
return mv88e6xxx_port_write(chip, port,
return mv88e6xxx_port_write(chip, port,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
err = mv88e6xxx_port_write(chip, MV88E6XXX_PORT_RESERVED_1A_DATA_PORT,
return mv88e6xxx_port_write(chip, MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT,
err = mv88e6xxx_port_write(chip, MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT,