mult_frac
capacity = mult_frac(max_capacity, capped_freq, max_freq);
nmul = mult_frac(rate, 1, parent_rate);
tmprate = mult_frac(parent_rate, nmul, 1);
rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
rate = mult_frac(rate, divt, divb);
ret = mult_frac(scale, duty->num, duty->den);
sys_freq = mult_frac(in_freq, mul, sys_div);
cpu_freq = mult_frac(in_freq, mul, cpu_div);
rate = mult_frac(rate, 2, hid_div + 1);
rate = mult_frac(rate, m, n);
*n = mult_frac(multiplier * *n, *pre_div, pre_div_max);
scaled_parent_rate = mult_frac(scaled_parent_rate, m, (m + 1));
parent_rate = mult_frac(req_rate, div, 2);
actual_rate = mult_frac(parent_rate, 2, div);
parent_rate = mult_frac(rate, div, 2);
actual_rate = mult_frac(parent_rate, 2, div);
return mult_frac(parent_rate, 2, div + 1);
return mult_frac(parent_rate, 1000, (div * 1000) + frac);
mult_frac(max_capacity, capped_freq, max_freq);
freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
adj_timeout_ms = mult_frac(timeout_ms, 3, 4);
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
ring_freq = mult_frac(gpu_freq, 5, 4);
mult_frac(src_height, 1, dst_height) : 1;
mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
phasex_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
phasey_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
*out_phase = mult_frac(unit, src, dst);
return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal);
pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes);
pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes);
msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8);
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
mult_frac(ref_clk, sdm_freq_seed, BIT(16));
new_value = 8192 + mult_frac(value - 8192, max_range, range);
value[0] = mult_frac((JC_IMU_PREC_RANGE_SCALE *
value[1] = mult_frac((JC_IMU_PREC_RANGE_SCALE *
value[2] = mult_frac((JC_IMU_PREC_RANGE_SCALE *
int calib_data = mult_frac(ds->gyro_calib_data[i].sens_numer,
int calib_data = mult_frac(ds->accel_calib_data[i].sens_numer,
int calib_data = mult_frac(ds4->gyro_calib_data[i].sens_numer,
int calib_data = mult_frac(ds4->accel_calib_data[i].sens_numer,
*val = mult_frac((long)sign_extend32(regval, 15), res, 1000000);
*val = mult_frac((long)regval, res, 1000000);
st->act_threshold = mult_frac(st->act_threshold,
st->inact_threshold = mult_frac(st->inact_threshold,
val = mult_frac(st->vref_mv, MICRO, st->gain_milli);
*val = mult_frac(st->vref_mv, 1, 10);
range = mult_frac(st->vref_uv, adaq4216_hw_gains_frac[i][1],
tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc3_filt_fs_tbl[i]);
tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc5_filt_fs_tbl[i]);
*val = mult_frac(st->vref_mv, MILLI,
val = mult_frac(st->vref_uv, d, n);
decimal = ((mult_frac(div, KILO, freq_khz) - dec * KILO) << 16)
fs = mult_frac(fs, 105, 100);
vcm_comp = 1050 + mult_frac(i, 450, 8);
vib->level += mult_frac(VIB_MAX_LEVELS(vib), vib->speed, MAX_FF_SPEED);
mem = (__u64)mult_frac(totalram_pages() - totalhigh_pages(),
if (mem > mult_frac(VMALLOC_TOTAL, DM_BUFIO_VMALLOC_PERCENT, 100))
mem = mult_frac(VMALLOC_TOTAL, DM_BUFIO_VMALLOC_PERCENT, 100);
c->bandwidth_hz = mult_frac(c->symbol_rate, rolloff, 100);
u32 delay = mult_frac(1000000UL, data->frame_interval.numerator,
vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
limit = mult_frac(device_pebs, max_beb_per1024, 1024);
if (mult_frac(limit, 1024, max_beb_per1024) < device_pebs)
val->intval = mult_frac(ret, chip_info->ibat_resolution_pv, info->rsnsb);
val->intval = 10000u * mult_frac(regval, 100000u, info->rsnsb);
value = mult_frac(value, info->rsnsb, 100000u);
voltage = 2000000 + mult_frac(regval, 1000000, 105);
regval = mult_frac(value, info->rsnsi, 50000u);
regval = mult_frac(value, info->rsnsb, 14660u);
jdelay = mult_frac(USER_HZ * jdelay, HZ, denom * USER_HZ);
#define SG_DEFAULT_TIMEOUT mult_frac(SG_DEFAULT_TIMEOUT_USER, HZ, USER_HZ)
if (val >= mult_frac((s64)INT_MAX, USER_HZ, HZ))
val = min_t(s64, mult_frac((s64)INT_MAX, USER_HZ, HZ),
sfp->timeout = mult_frac(val, HZ, USER_HZ);
thres = mult_frac(bwmon_kbps_to_count(bwmon, kbps),
window = mult_frac(bwmon->data->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC);
bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->data->sample_ms);
timeout = mult_frac(bytes, 2 * 8 * MSEC_PER_SEC,
dev->dev_attrib.hw_max_sectors = mult_frac(queue_max_hw_sectors(q),
io_max_blocks = mult_frac(dev->dev_attrib.hw_max_sectors,
temp = temp_hi + mult_frac(temp_lo - temp_hi, val - adc_hi,
vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
return mult_frac(val, sysctl_vfs_cache_pressure, sysctl_vfs_cache_pressure_denom);
dentries = mult_frac(sc->nr_to_scan, dentries, total_objects);
inodes = mult_frac(sc->nr_to_scan, inodes, total_objects);
fs_objects = mult_frac(sc->nr_to_scan, fs_objects, total_objects);
tmp = mult_frac(tmp, data, term->divider);
return mult_frac(access_events, 10000, target_access_events);
quota->charged_sz += sz_applied + mult_frac(
return mult_frac(numerator, 10000, i.totalram);
return mult_frac(numerator, 10000, i.totalram);
return mult_frac((unsigned long)node_eligible, 10000,
return mult_frac(active, 10000, total);
return mult_frac(inactive, 10000, total);
mult_frac(goal->current_value, 10000,
throughput = mult_frac(quota->total_charged_sz,
return mult_frac(nr_accesses, 10000, damon_max_nr_accesses(attrs));
res = mult_frac(abs(val), unit, PAGE_SIZE);
max_boost = mult_frac(zone->_watermark[WMARK_HIGH],
mult_frac(zone_managed_pages(zone),
x = mult_frac(x, n->nr_partial, scanned);
return mult_frac(nr_freeable, nr_backing, nr_stored);