mtk_w32
mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
mtk_w32(eth, eth->soc->rx.irq_done_mask,
mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
mtk_w32(eth,
mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
mtk_w32(eth, ring->phys,
mtk_w32(eth, rx_dma_size,
mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
mtk_w32(eth, ring->phys,
mtk_w32(eth, rx_dma_size,
mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
mtk_w32(eth, val, reg);
mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, val, reg_map->qdma.glo_cfg);
mtk_w32(eth,
mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id));
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
mtk_w32(eth, val, reg_map->pdma.delay_irq);
mtk_w32(eth, val, reg_map->qdma.delay_irq);
mtk_w32(eth, val, reg_map->pdma.delay_irq);
mtk_w32(eth, val, reg_map->qdma.delay_irq);
mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
mtk_w32(eth, PHY_IAC_ACCESS |
mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
mtk_w32(eth, val, MTK_MAC_MCR(i));
mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
mtk_w32(eth, TRGMII_MODE, INTF_MODE);
mtk_w32(mac->hw,
mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
mtk_w32(eth, val, MTK_MAC_EEECR(mac->id));
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
mtk_w32(pctl, i, reg, val);
mtk_w32(rtc, reg, val);
mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
mtk_w32(hw, MTK_RTC_AL_CTL, 0);
mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);