drivers/gpu/drm/mediatek/mtk_ddp_comp.c

137

mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

138

mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

139

mtk_ddp_write(cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

144

mtk_ddp_write(cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

150

mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

160

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

161

mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

226

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

227

mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

244

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

246

mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

356

void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_disp_aal.c

77

mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_aal.c

78

mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

103

mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

105

mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

107

mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

109

mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

111

mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

63

mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

65

mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,

drivers/gpu/drm/mediatek/mtk_disp_color.c

66

mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color));

drivers/gpu/drm/mediatek/mtk_disp_color.c

67

mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color));

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

219

mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_merge.c

100

mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

103

mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

113

mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

156

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

158

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

160

mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

170

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

173

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

176

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

183

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

185

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

88

mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

91

mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

330

mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

331

mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

376

mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

387

mtk_ddp_write(cmdq_pkt, gmc_value,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

400

mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

213

mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

288

mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

178

mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

206

mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

208

mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

209

mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

228

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

231

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

234

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

237

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

240

mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

243

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);

drivers/gpu/drm/mediatek/mtk_ethdr.c

244

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);

drivers/gpu/drm/mediatek/mtk_ethdr.c

245

mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);

drivers/gpu/drm/mediatek/mtk_ethdr.c

246

mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);

drivers/gpu/drm/mediatek/mtk_ethdr.c

247

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

249

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

251

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

253

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

255

mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));

drivers/gpu/drm/mediatek/mtk_ethdr.c

256

mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

174

mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

175

mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);