CMD_REG
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
.write_flag_mask = CMD_REG | CMD_WRITE,
.read_flag_mask = CMD_REG,
tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
ctx->buf[0] = (reg & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
ctx->buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
outb(CHIP_RESET, io_port + CMD_REG);
outb(SCSI_NOP, io_port + CMD_REG); /* required after reset */
outb(SCSI_RESET, io_port + CMD_REG);
outb(FLUSH_FIFO, port_base + CMD_REG);
outb(TRANSFER_INFO | DMA_OP, port_base + CMD_REG);
outb(FLUSH_FIFO, port_base + CMD_REG);
outb(TRANSFER_INFO | DMA_OP, port_base + CMD_REG);
outb(FLUSH_FIFO, port_base + CMD_REG);
outb(INIT_CMD_COMPLETE, port_base + CMD_REG);
outb(SET_ATN, port_base + CMD_REG); /* Reject the message */
outb(MSG_ACCEPT, port_base + CMD_REG);
outb(SET_ATN, port_base + CMD_REG); /* Reject message */
outb(MSG_ACCEPT, port_base + CMD_REG);
outb(FLUSH_FIFO, port_base + CMD_REG); /* reset the fifos */
outb(SELECT_NO_ATN, port_base + CMD_REG);