arch/x86/events/amd/brs.c

47

native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3);

arch/x86/hyperv/hv_crash.c

104

native_wrmsrq(HV_X64_MSR_RESET, 1); /* get hyp to reboot */

arch/x86/hyperv/ivm.c

122

native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val);

arch/x86/include/asm/apic.h

213

native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK);

arch/x86/include/asm/microcode.h

68

native_wrmsrq(MSR_IA32_UCODE_REV, 0);

arch/x86/include/asm/msr.h

137

native_wrmsrq(msr, val);

arch/x86/include/asm/spec-ctrl.h

87

native_wrmsrq(MSR_IA32_SPEC_CTRL, val);

arch/x86/kernel/apic/x2apic_savic.c

336

native_wrmsrq(MSR_AMD64_SAVIC_CONTROL, 0);

arch/x86/kernel/apic/x2apic_savic.c

368

native_wrmsrq(MSR_AMD64_SAVIC_CONTROL,

arch/x86/kernel/cpu/mce/core.c

1349

native_wrmsrq(MSR_IA32_MCG_STATUS, 0);

arch/x86/kernel/cpu/microcode/amd.c

702

native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr);

arch/x86/kernel/cpu/microcode/intel.c

667

native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);

arch/x86/kernel/cpu/mshyperv.c

92

native_wrmsrq(reg, sint.as_uint64);

arch/x86/kernel/cpu/mshyperv.c

95

native_wrmsrq(reg, value);

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

166

native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);

arch/x86/kvm/vmx/vmx.c

415

native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);

arch/x86/kvm/vmx/vmx.c

482

native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr);

arch/x86/kvm/vmx/vmx.c

493

native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);

arch/x86/kvm/vmx/vmx.c

7519

native_wrmsrq(MSR_IA32_SPEC_CTRL, hostval);