arch/x86/boot/startup/sme.c

528

sev_status = msr = native_rdmsrq(MSR_AMD64_SEV);

arch/x86/boot/startup/sme.c

559

msr = native_rdmsrq(MSR_AMD64_SYSCFG);

arch/x86/coco/sev/internal.h

75

return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB);

arch/x86/events/amd/brs.c

52

return native_rdmsrq(MSR_AMD_DBG_EXTN_CFG);

arch/x86/hyperv/hv_vtl.c

165

input->vp_context.efer = native_rdmsrq(MSR_EFER);

arch/x86/hyperv/hv_vtl.c

169

input->vp_context.msr_cr_pat = native_rdmsrq(MSR_IA32_CR_PAT);

arch/x86/hyperv/ivm.c

117

return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB);

arch/x86/include/asm/mshyperv.h

238

return native_rdmsrq(reg);

arch/x86/kernel/cpu/common.c

176

c->ppin = native_rdmsrq(info->msr_ppin);

arch/x86/kernel/cpu/mce/core.c

125

m->mcgcap = native_rdmsrq(MSR_IA32_MCG_CAP);

arch/x86/kernel/cpu/mce/core.c

1341

mcgstatus = native_rdmsrq(MSR_IA32_MCG_STATUS);

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

165

saved_msr = native_rdmsrq(MSR_MISC_FEATURE_CONTROL);

arch/x86/kvm/vmx/vmx.c

480

msr = native_rdmsrq(MSR_IA32_MCU_OPT_CTRL);

arch/x86/kvm/vmx/vmx.c

7508

vmx->spec_ctrl = native_rdmsrq(MSR_IA32_SPEC_CTRL);