mxl111sf_write_reg
ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_0, tmp);
ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_1, tmp);
ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_2, tmp);
ret = mxl111sf_write_reg(state, 0x19, tmp);
ret = mxl111sf_write_reg(state, 0x30, tmp);
ret = mxl111sf_write_reg(state, 0x17, r17);
ret = mxl111sf_write_reg(state, 0x18, r18);
ret = mxl111sf_write_reg(state, 0x12, r12);
ret = mxl111sf_write_reg(state, 0x15, r15);
ret = mxl111sf_write_reg(state, 0x82, r82);
ret = mxl111sf_write_reg(state, 0x84, r84);
ret = mxl111sf_write_reg(state, 0x89, r89);
ret = mxl111sf_write_reg(state, 0x3D, r3D);
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);
ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);
ret = mxl111sf_write_reg(state,
ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);
ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);
ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);
ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);
ret = mxl111sf_write_reg(state, 0x00, 0x02);
ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);
ret = mxl111sf_write_reg(state, 0x00, 0x00);
ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,
ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);
ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */
ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */
ret = mxl111sf_write_reg(state, 0x03,
return mxl111sf_write_reg(state, 0x01, onoff ? 0x01 : 0x00);
ret = mxl111sf_write_reg(state, addr, val);
.write_reg = mxl111sf_write_reg,
.write_reg = mxl111sf_write_reg,
int mxl111sf_write_reg(struct mxl111sf_state *state, u8 addr, u8 data);