mxl111sf_read_reg
ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_0, &tmp);
ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_1, &tmp);
ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_2, &tmp);
ret = mxl111sf_read_reg(state, 0x17, &r17);
ret = mxl111sf_read_reg(state, 0x18, &r18);
ret = mxl111sf_read_reg(state, 0x12, &r12);
ret = mxl111sf_read_reg(state, 0x15, &r15);
ret = mxl111sf_read_reg(state, 0x82, &r82);
ret = mxl111sf_read_reg(state, 0x84, &r84);
ret = mxl111sf_read_reg(state, 0x89, &r89);
ret = mxl111sf_read_reg(state, 0x3D, &r3D);
ret = mxl111sf_read_reg(state, 0x19, &tmp);
ret = mxl111sf_read_reg(state, 0x30, &tmp);
ret = mxl111sf_read_reg(state, 0x23, &tmp);
ret = mxl111sf_read_reg(state, 0x2f, &tmp);
ret = mxl111sf_read_reg(state, 0x22, &tmp);
ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &b);
ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode);
ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);
ret = mxl111sf_read_reg(state,
ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);
ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);
ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);
ret = mxl111sf_read_reg(state, addr, &val);
ret = mxl111sf_read_reg(state, addr, &val);
ret = mxl111sf_read_reg(state, CHIP_ID_REG, &id);
ret = mxl111sf_read_reg(state, TOP_CHIP_REV_ID_REG, &ver);
.read_reg = mxl111sf_read_reg,
.read_reg = mxl111sf_read_reg,
int mxl111sf_read_reg(struct mxl111sf_state *state, u8 addr, u8 *data);