mt7601u_wr
mt7601u_wr(dev, MT_TX_PWR_CFG_7, val);
mt7601u_wr(dev, MT_TX_PWR_CFG_9, val);
mt7601u_wr(dev, MT_TX_PWR_CFG_0 + i * 4, val);
mt7601u_wr(dev, MT_USB_DMA_CFG, val);
mt7601u_wr(dev, MT_USB_DMA_CFG, val);
mt7601u_wr(dev, MT_USB_DMA_CFG, val);
mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
mt7601u_wr(dev, MT_MAC_SYS_CTRL,
mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
mt7601u_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]);
mt7601u_wr(dev, MT_BEACON_TIME_CFG, val);
mt7601u_wr(dev, MT_MAX_LEN_CFG, 0xa0fff |
mt7601u_wr(dev, MT_WCID_ATTR(idx), val);
mt7601u_wr(dev, MT_LEGACY_BASIC_RATE, info->basic_rates);
mt7601u_wr(dev, MT_HT_FBK_CFG0, 0x65432100);
mt7601u_wr(dev, MT_HT_FBK_CFG1, 0xedcba980);
mt7601u_wr(dev, MT_LG_FBK_CFG0, 0xedcba988);
mt7601u_wr(dev, MT_LG_FBK_CFG1, 0x00002100);
mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val);
mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN |
mt7601u_wr(dev, 0x94c, 0);
mt7601u_wr(dev, MT_FCE_PSE_CTRL, 0);
mt7601u_wr(dev, 0xa44, 0);
mt7601u_wr(dev, 0x230, 0x84210);
mt7601u_wr(dev, 0x400, 0x80c00);
mt7601u_wr(dev, 0x800, 1);
mt7601u_wr(dev, MT_FCE_PSE_CTRL, 1);
mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN |
mt7601u_wr(dev, MT_USB_DMA_CFG, val);
mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230);
mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 1);
mt7601u_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44);
mt7601u_wr(dev, MT_FCE_SKIP_FS, 3);
void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val);
return mt7601u_wr(dev, offset, val);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);
mt7601u_wr(dev, MT_BBP_CSR_CFG,
mt7601u_wr(dev, MT_BBP_CSR_CFG,
mt7601u_wr(dev, MT_RF_CSR_CFG,
mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |
mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);
mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);
mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);
mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);
mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);
mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
mt7601u_wr(dev, MT_RF_CSR_CFG,
mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
mt7601u_wr(dev, MT_RF_SETTING_0, 0);
mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);
mt7601u_wr(dev, offset, get_unaligned_le32(addr));
mt7601u_wr(dev, offset + 4, addr[4] | addr[5] << 8);