mvreg_write
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
mvreg_write(pp, MVNETA_RXQ_CMD,
mvreg_write(pp, MVNETA_TXQ_CMD,
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
mvreg_write(pp, MVNETA_INTR_NEW_MASK,
mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
mvreg_write(pp, MVNETA_ACC_MODE, val);
mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
mvreg_write(pp, MVNETA_PORT_CONFIG, val);
mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
mvreg_write(pp, MVNETA_INTR_ENABLE,
mvreg_write(pp, MVNETA_TX_MTU, val);
mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
mvreg_write(pp, MVNETA_TYPE_PRIO, val);
mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
mvreg_write(pp, MVNETA_INTR_NEW_MASK,
mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
mvreg_write(pp, MVNETA_SERDES_CFG,
mvreg_write(pp, MVNETA_SERDES_CFG,
mvreg_write(pp, MVNETA_SERDES_CFG,
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, an);
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER,
mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, clk);
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi1);
mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi0);
mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi1);
mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
mvreg_write(pp, MVNETA_PORT_CONFIG, val);
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
mvreg_write(pp, MVNETA_WIN_BASE(i),
mvreg_write(pp, MVNETA_WIN_SIZE(i),
mvreg_write(pp, MVNETA_WIN_BASE(0),
mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);